problem synthesizing for loop

[zubairbasha]

i am using CADENCE TOOlS

nclaunch for verilog(rlt) code
rc-compailer for synthesis

in one of my code i am using for loop... shown below

for(ST =1'b0;bk1>8'b0;ST =1'b0 )
begin
bk1 = bk1>>1;
if(bk1[0]==1) ST_ODD = ST_ODD+1;
else ST_ODD = ST_ODD;
end
next_state = s2;




in rc complier the following ERROR is generated...........

Elaborating top-level block 'encoding_technique1' from file '/root/rclabs/work/../rtl_mini_project/mini_project.v'.
Error : Reached maximum loop limit while unrolling loop. [CDFG-457] [elaborate]
: Loop maximum = 1024 in file '/root/rclabs/work/../rtl_mini_project/mini_project.v' on line 82.
Info : Deleting HDL design. [CDFG-305]
: Design 'encoding_technique1'.
Module 'encoding_technique1' contains errors and cannot be elaborated.



i gave following command in my sdc file

*********************************
set_attribute hdl_max_loop_limit 5000
*********************************

still i failed to elaborate my code

what i understood is though my iterations are at mamxium 512 which is with in max limit of 1024 still i am unable to synthesis my code
can any one make me understand the mistake i am doing here.

Thanks in advance

 

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You need to read up on the Verilog for loop. It's not a SW construct where you can modify the loop variable on the fly while running the code in a simulator. It's meant for producing parallel hardware.