error for my vhdl design

[gholamzadeh]

hi
i wrote a vhdl code for read and write from sd card,and i have a problem,this error deny me to synthesize this code in xilinx

ERRORack:18 - The design is too large for the given device and package.
ERROR: MAP failed

I do not know how little of its size
please help me
thanx

 

[Er.abdulrehman]

you had not selected proper target device, as your code may contain large amount of IO'S, Slices,etc, so select proper device else optimize you code