hai....... i am trying code for serial in parallel out .

[ramana]

i got error at "=" please help me

module sipo12(d,c,r,q);
input d,c,r;
output [2:0]q;
reg [2:0]q;
always @(negedge c);
begin
if(r)
q=3'b000;
else begin q[2]=d;
q[1]=q[2];
q[0]=q[1];end
end

 

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Some suggestions...

1. Use Verilog 2001 module port declarations
2. use something other than 1 character names (the sooner you learn that habit the sooner others will no longer curse your name/code when they have to take it over when your gone)
3. don't use = (blocking assignments) in a clocked always block use <= (non-blocking). As written your code won't perform a shift operation.
4. use posedge clk unless you've got a good reason for using the negative edge.
5. use good formatting to make code readable/maintainable

---

Code Verilog - [expand]
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module sipo (
  input d_in,
  input clk,
  input rst,
  output reg [2:0] q_out
);
 
  always @ (posedge clk) begin
    if (rst) begin
      q_out <= 3'b0;
    end else begin
      q_out <= {d_in, q_out[2:1]};
    end
  end
 
endmodule

---

If you need q_out to update only after 3-bits have been shifted in then you'll need a separate shift register instead of directly using q_out and a counter to keep track of the number of shifts. The q_out value will then be updated on the count of 2'b10 (count of 0-2).

 

[LawrenceC]

I think the error is on the always @ line. There should not be a ';' at the end of that line.

 

[arishsu]

Don't use blocking assignnents in synchronous ckts. This will update all the output bits q[0],q[1] and q[2] to the same value 'd'.