USB Blaster download cable design

[bcarson]

usb blaster ftd2xx.sys

Hi
Here you can refer to the answers.

Could you please describe the differences in more detail?!
What do you mean by "disconnected" - the adapter itself or the target?

--> USB-BLASTER ( with your CPLD design ) is disconnected from target board.

PC(Quartus II ) --o-- USB-BLASTER ---x--- target board


How long does it take with the one or the other adapter?

--> about 10 sec when with USB-BLASTER ( with your CPLD design)
--> less than 1 sec when with USB-BLASTER (from ALTERA )

Why do you think it is "too" long?
--> I think JTAG disconnection or reverse sided header insertion should be reported quickly when attempting downloading SOF file to FPGA.

Are you using the CPLD or the FX2 variant?

--> CPLD variant
If you're using the CPLD variant, what clock are you using?
--> 24MHz


Thanks & Best regards,
Bcarson

 

[kawk]

program max + usb blaster +altera

Hi,

Yes, 10 vs 1 sec is really long. I'm not sure whether Quartus could quickly determine whether a target is connected (and powered) from the idle state of the input pins (TDO and ASDI) at the CPLD. The may have a different logic level when the output drivers are active and a target is connected (even if there was no JTAG activity).

I'm not at the place where I could take a look myself for a while, so at this time I have no further suggestions, sorry

Kolja

 

[bcarson]

usb blaster+output enable

Hi Kawk,
At normal state ( when Power and the connection with target board are normal), your USb-BLASTER design works excellently.
Pls don't worry about the code revision which I required you. You did a very good job.

Thanks and Best Regards,
Bcarson

 

[damn]

altera usb blaster 6 pin adapter

check it in jtag mode, with ps mode

 

[Nick18]

usb blaster driver c++ altera

Is there also an option to program Lattice devices? Greetz Nick

 

[will_frost]

expected jtag id

can be programed to a xilinx cpld?

 

[kawk]

xilinx platform cable usb schematics

Hi,

Can Xilinx CPLD be used instead of Altera CPLD to build the cable?

the CPLD design should work in a Xilinx chip as well as in an Altera. But I'm not sure whether the state machine encoding works as well as when synthesized with Altera tools - there is no explicit reset signal; this works only reliably because there are no unused states. Make sure that it is not synthesized as one-hot but with a 4 bit encoding. Or add an asynchronous reset signal from somewhere to be able to reset the state machine once after booting (this would need additional external circuitry)

Can it be used to program Lattice devices?

in theory you could also program Lattice devices with this JTAG adapter. But it is not directly compatible with Lattice ispVM or other Lattice-specific programming software. So you first would have to check whether the _software_ that is compatible with my cable can be used to program Lattice devices: openwince JTAG tools or OpenOCD. They have SVF players, maybe that could be used for Lattice targets.

I'm on the other hand working on a more flexible host software named UrJTAG which will be able to program Lattice devices too. But it's far from being usable. Planning can be checked at http://urjtag.sf.net/

BTW, the Lattice USB cable is similar (but not compatible) to the Xilinx XPCU, being based on FX2 and a (Lattice MachXO) CPLD. If I had one here for evaluation I could probably make a firmware that emulates an USB-Blaster - just as I did for the Xilinx cable (but that's not what you where asking for, I know )

Kolja

 

[will_frost]

platform cable usb driver usb-blaster

Hi, kawk

I have programed your code into a xilinx cpld(xc9572xl) but it doesn't work, do you konw why?

 

[kawk]

usb blaster update cpld

Unless you tell us more about what you did and what problems you experience, the answer can be only "No". From your short question, I can't know anything about your experience level, and therefore a good answer might be anything from "maybe the power is connected with reversed polarity" to "maybe the state machine doesn't always start up properly because the statements or assignments or configuration needed to ensure 4-bit encoding with Xilinx tools is different, did you check that"? What tools do you have available for debugging, and what did you try already? Is it a homebrew circuit with some flying wires or a commercial grade board? Kolja

 

[miniK0bo]

usb blaster +5v epm7064s

I've tried your firmware for the FX2 variant, changed pid, vid en the string. Quartus recognized the USB-blaster and detects my fpga successfully! But, when I try to program a error occurs:

Error: Can't configure device. Expected JTAG ID code 0x020B20DD for device 1, but found JTAG ID code 0x00000000.
Error: Operation failed

The programming stops at 47%-49%. My config done led goes on. After this error I cannot detect my fpga anymore, I get the the following error message:

Error: Can't access JTAG chain
Error: Operation failed

any suggestions?

edit: more info added

 

[kawk]

altera usb blaster pull up resistor circuit

Hi,

The programming stops at 47%-49%. My config done led goes on.

Are you sure the device type is configured correctly in Quartus? Does it always occur at the same percentage? Looks like if it's transmitting too much data to the FPGA.

Or - it transmits the correct amount of data, but the FPGA detects more clock pulses than there actually are. Therefore, I guess it's a problem with overshooting on the TCK line or the like. Do you have correct pullups/pulldown resistors in place? Short cables?

Regards,
Kolja

 

[naohto]

ft245bl logic analyzer

Hi, KAWK

I have tested your CPLD variant on my CycloneIII EP3C25.
- In JTAG mode, it work very well.
- However when I test in AS mode with EPCS16, it can program but fail to verify.
- I have tried to use 1MHz CLK, it work!! but doesn't auto reset the device when finish the programming process.
- Please suggest, why it fail (only verify in AS mode) when use 24 MHz.

Note
I have tested my CycloneIII board with ByteBlasterII, it can program, verify and auto reset the device when finish the programming process.

Thanks

 

[FvM]

usb blaster schematic diagram

Hello,

AS programming is known to be critical also with original USB Blaster. Thus it must not necessarily be an issue of CPLD defined timing. I didn't check, if the project Blaster is equivalent regarding AS timing. Basically, as far as I know from original device, bit timing is identical for JTAG and AS.

It also could be a driver issue, you should use a short cable for AS programming, with above 20 cm cable, also Byteblaster AS programming could fail according to my experience.

Regards,
Frank

 

[yakex]

cyclone ii usb blaster driver

hi,
have one succeed in cloning or builting a usb download cable for Xilinx FPGA?
Thanks

 

[tube]

produse puls with vhdl

I am interested in such xilinx cable,too.

 

[hitajian]

vid_09fb&pid_6001

It seems there are many xilinx compatible usb download cable in the market . So some guys have cloned it successfully.

 

[davorin]

altera usb-blaster urjtag

Thought I share my experience with building an USB Blaster based on FX2LP from Cypress...

As I already got an USB Cable from Lattice which uses the same chip, although 100 pins, I removed the SDA pin from it so I can download own firmware for testing...

First off...get it recognized by Quartus as an USB Blaster....you have to know that changing VID/PID isn't enough....so here is the USB description "dscr.a51" from this project:

http://www.ixo.de/info/usb_jtag/

Dunno anything about Xilinx USB cables...but at least it looks we culd easily build a combined Lattice/Altera cable (o;

 

[FvM]

altera usb blaster equivalent

I didn't clearly understand from your post, if you also managed to operate the Cypress solution as an USB Blaster, including the Altera specific parallel-to-serial coding in the CPLD. Particularly I'm not sure if the FX2LP achieves a data flow control compatible with FTD2XX driver.

P.S.: When reviewing the UrJTAG project, I understood that it's achieving the USB Blaster specfic function in software. I didn't yet see, if it has proven fully compatible, and am not sure regarding the performance. Original USB Blaster can be expected to stream bulk data with nearly full rate of 6 MBit/s. Most Altera FPGA would support higher JTAG speed. About the FX2 solution?

 

[davorin]

download drivers for usb blaster

I'm also not familiar yet with the whole source code yet (o;

Just used the Lattice USB cable for verifying the source code and how to adapt it for hardware changes...

At least I can progam with it my Cyclone devices without problems now as I don't have any PC anymore with LPT port...

I'm sure it is not 100% compatible to the original one...and I'm not able to verify it as I don't have one to compare to...maybe my FAE will lend me one (o;

 

[kawk]

linux altera usb-blaster

Hi,

I didn't yet see, if it has proven fully compatible, and am not sure regarding the performance. Original USB Blaster can be expected to stream bulk data with nearly full rate of 6 MBit/s. Most @ltera FPGA would support higher JTAG speed. About the FX2 solution?

The maximum bit rate is 3 MHz with the FX2, but because it also has to handle the USB protocol in software, the maximum througput is probably less. In daily work it appears to be "a little slower" than an USB-Blaster.

Kolja