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Sinewave inverter prototype...

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i know, but 14V*30 is 420V. or you may change transformer ratio to 26 and use 400V TVS.
 

whats about wave form after irf 740 it remain same or change ?
 

wave is remain sine, but amplitude is lower, especially if battery discharged
 

hi again,
would i use 5.6k or 4.7k instead of 5.1k as it not available here ?
 

yes, but if that resistors stay in voltage divider its pair must be accordingly changed
 

full version of microprogram for circuit from #334
 

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  • M8DIP_c&hex.zip
    13.2 KB · Views: 240

hi ,
i really appreciated your work . but i'm unable to test on actual hardware due to non availability of components :( the only mcu available here are attiny13 and mega8 dip version.

i notice that in previous post like #319 you use sine table after that you didn't use any more any specific reason ?
 
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mega8 and similar mcu is capable to calculate this table themselves during initialization process. this deprives some amount of memory, but allows easy switching between different mcu and output frequencies.
 

Which do you think is better for SPWM stm8, mega8, attiny13 ?..
What program do you use to access programming an STM8 , keil , iar v.s.

translated by google...
 

hi ,
i test #348 code in proteus no signal from pb1 and pb2 .
 

that is version with overcurrent and low battery protection, so it is necessary to connect PC.0 (ADC0) and PD.7 (AIN1) and AVCC to +5V. and also ADC1 to gnd.
 
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in that case why signal generate from pb3 and pb4 ?
 

why signal generate
because this is slightly simple decision.
________________________________________
next prototype - 3 phase 50...400Hz DCAC converter, not tested
 

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  • stm8 3p c&hex&pcb.zip
    88.3 KB · Views: 184

200Hz 3 phase square wave output DCAC converter, for 36V 200Hz sheep trimmer )
 

Attachments

  • stm8s103f2p6 3ph c hex pcb.zip
    56 KB · Views: 157

The most critical part by far on this last design is ferrite transformer losses and turns ratio. litz wire is preferred and low loss ferrite.

With RdsOn of 6mΩ or 12 mΩ in full bridge and at least a turns ratio of 330/11=30x , the source to output impedance becomes 900x12mΩ ~11Ω, plus conduction losses P=I²(R+kωL) in transformer with k being an Eddy current loss function and margin to saturation, which may increase Zeff to 15 to 30Ω if you aren't careful in T design.

then if output bridge only conducts 5% of the time for 5% ripple, the impedance multiplies by another 20x and becomes very sensitive to load regulation... Or 1% ripple becomes 100x source Output Z
 

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