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hi ,
i really appreciated your work . but i'm unable to test on actual hardware due to non availability of components the only mcu available here are attiny13 and mega8 dip version.
i notice that in previous post like #319 you use sine table after that you didn't use any more any specific reason ?
mega8 and similar mcu is capable to calculate this table themselves during initialization process. this deprives some amount of memory, but allows easy switching between different mcu and output frequencies.
that is version with overcurrent and low battery protection, so it is necessary to connect PC.0 (ADC0) and PD.7 (AIN1) and AVCC to +5V. and also ADC1 to gnd.
The most critical part by far on this last design is ferrite transformer losses and turns ratio. litz wire is preferred and low loss ferrite.
With RdsOn of 6mΩ or 12 mΩ in full bridge and at least a turns ratio of 330/11=30x , the source to output impedance becomes 900x12mΩ ~11Ω, plus conduction losses P=I²(R+kωL) in transformer with k being an Eddy current loss function and margin to saturation, which may increase Zeff to 15 to 30Ω if you aren't careful in T design.
then if output bridge only conducts 5% of the time for 5% ripple, the impedance multiplies by another 20x and becomes very sensitive to load regulation... Or 1% ripple becomes 100x source Output Z
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