Phase Shift Full Bridge SMPS is massively over-hyped?

[Easy peasy]

Which “diodes to the rails” are you speaking of may I ask?

it's in the quote you copied:

where this choke connects to the Tx

please read more carefully, this is a common device on high power FB FS converters...

And, its not plainly shown that raising Llk has no effect on converter losses, you have performed a simulation which any real power engineer knows is some way from reality, if/when you build a high power hard switched full bridge you will discover a great many things that a sim does not reveal, unfortunately it may well be too late at that point to convert what you have into a sale-able converter that passes EMC...

 

[treez]

The simulator (as attached) shows that indeed adding "diodes to the rails" in between the external 'leakage' inductor and the transformer, does indeed slightly reduce the snubber dissipation. -Not by much, but a reduction, a reduction of some 16%.

I cannot help but think that the addition of such “diodes to the rails” in a PSFB is going to have a detrimental impact at lighter loading The whole point of that external (‘leakage’) inductor is to get it in the flow of the magnetising current, to get its current up, so that it can instigate ZVS, ..by adding these “diodes to the rails”, its allright when heavily loaded, but at lighter load, those “diodes to the rails” are providing a discharge path to that external inductor, a discharge which wont be wanted, and could deteriorate performance at light load.

As we know, there is always a “sting in the tail” to adding components like that..for example, the aforementioned “caps across the FETs”, have their advantages, but in certain conditions, have marked disadvantages.

 

[Easy peasy]

Hmmm, its interesting that you know so much about Phase Shift FB converters without ever having built one, perhaps there are other advantages to having the extra diodes which are completely non obvious....?
BTW the 7.5kW PSFB converters we have, have 4W of snubbing on each of the 2 output diodes for full power (65V 130A), below full power the snubbers contribute to lower dv/dt which allows easier EMC filtering....

p.s. your 3uH might be a little light for practical design...

 

[treez]

..thanks, with an increased external inductor (to 22uH), the power loss in the diode snubbers is significantly reduced when the "diodes to the rails" are present...as the attached LTspice simulation shows. (50% less snubber dissipation in the PSFB with "diodes to the rails")
Of course, with "diodes to the rails" included , it becomes significant on which side of the transformer the external inductor is connected. If connected to the "passive leg" side, then there is more duty cycle loss, and a resultant lower output voltage of the PSFB.

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Clearly post #38 (quote near the bottom) shows us that if the PSFB is to be implemented in anything other than constant, non-dynamic load situations, then the prototype PSFB unit will first need to undergo a serious, lengthy “reverse recovery” tesing phase.
This is because (as the app note from infineon in post #38 says), the PSFB can potentially suffer disastrous reverse recovery of its primary side mosfet intrinsic diodes during light load, or load transients, and other conditions. This can result in latch-up of those FETs, destroying them in seconds.
This is a problem that you avoid completely by doing a plain full bridge converter.

The test jig for the prototype PSFB , would involve the PSFB being switched from no-load to full load every say 500 milliseconds, repeatedly, for days.
Then ditto but from 50% to 100% load for another period of days.
It would then involve the PSFB being left on no load for days.
Another test would then be done with the PSFB being repeatedly started up, then shut down, again for days.
-This would be done in two sets..
1...Start-up into no-load, then shut down again
2...Startup into full load, then shut down again.

Then again the PSFB would have to endure transient overloads, repeatedly, every 90 seconds, for days on end.
The above tests would need to be done with the worst case external inductor tolerance value. -Also, with the actual FETs that are intended for use, in the eventual product. Also, the series gate resistor should be the same as that that will be shipped in the intended product. If any of the above changes due to obselescence etc, than all these tests need to be done over again.

None of this testing would need doing with a full bridge..at least not to anywhere near the level of time required for the PSFB.

One may think that the reverse recovery of the PSFB’s primary side FETs could be prevented by paralleling ultra fast diodes across them..however, those UF diodes may well be of higher Vf than the intrinsic diodes in the FETs, meaning they would be ineffective in stopping reverse recovery of the PSFB’s intrinsic diodes of its primary fets.

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Here is just one article that looks into failure modes of Phase shift full bridge
http://www.irf.com/technical-info/whitepaper/s30p5.pdf
"failure modes of phase shift full bridge converter " in google reveals loads of similar

 

[treez]

[Moved]Inductor in series with Full bridge SMPS transformer is good idea?

Hello
We are doing a 300W full bridge converter. Vin=300 to 400VDC, Vout = 15V, F(sw)=120khz.
We would like to add a 10uH inductor in series with the transformer primary in order to reduce the overvoltage ring on the secondary diodes at FET switch on. Can you state why this does not appear to be a standard procedure, after all, it is an easy way of getting improvement with little or no downside.
(ltspice sim and schem attached)

 

[treez]

Hmmm, its interesting that you know so much about Phase Shift FB converters without ever having built one

Sorry indeed I haven't built one at high power, does anyone in UK?..We couldn't find anyone to do it for us for any price below half a million quid. In UK, nobody makes anything now, we are simply all suckling off the last remnants of North Sea Oil, until it runs out, then leaving the United Kingdom to slide inevitably into the third world.

 

[Easy peasy]

At 300W and 15V out it is easier to put snubbers on the o/p diodes... lower cost.

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From start to finish for 7.5kW 3 phase in, high voltage out, GBP 250,000 would seem about right, including EMC, all manufacture documentation and 3 units identical to manufacture, without any fancy control (i.e. uP front panel) or comm's

 

[treez]

thanks, does that 250k include schematic, Full BOM, Full transformer/inductor manufacturing specs, layout file in PCB program, schematic file in PCB program, layout file in ASCII format so it can be viewed in eg Valor? Also, can you give a rough time scale?
BTW, the requirement now is for 3.8kw from single phase mains, with 300-410vdc battery charging output, plus a 300w, 15v output off the battery.

 

[Easy peasy]

all manufacture documentation

does include " schematics, BOM's,magnetics build sheets & manufacturing specs, layout file in PCB program (Altium), schematic file in PCB program (Altium) & mechanical design drawings showing heat-sinking arrangements and overall case, test results showing temp rises of critical parts, safety summary showing CE requirements are met for isolation" and scans showing EMC results, about 8 months to provide the initial units, "paper work" to follow that.

 

[Easy peasy]

3.8kw from single phase mains, with 300-410vdc battery charging output, plus a 300w, 15v output off the battery.

even easier...
18 amps at 230Vac in requires a largish input stage but we have a nice interleaved solution with big fets and SiC diodes that delivers a cool booster.

 

[Mr.Cool]

just an idea, but what bout interleaving two smaller PSFB outputs into one to get the high(er) power you wanted? more parts, most cost, but you get to spread out the heat.

ps. a 5kW interleaved boost PFC front end is straight forward to design though i think you may have to wind your own inductor.
https://www.ti.com/tool/pmp4311

$0.02

 

[nrgize]

thanks, does that 250k include schematic, Full BOM, Full transformer/inductor manufacturing specs, layout file in PCB program, schematic file in PCB program, layout file in ASCII format so it can be viewed in eg Valor? Also, can you give a rough time scale?
BTW, the requirement now is for 3.8kw from single phase mains, with 300-410vdc battery charging output, plus a 300w, 15v output off the battery.

Hi, I just came across this thread looking for something else entirely on the web and got drawn in due to the subject matter. I don't usually contribute to forums so I hope my post is interesting and meets the expected standards!

I designed and build a 3.8kW single phase input power supply for on-board EV charging in 1993. This was before the days of SiC and I used non-interleaved CCM PFC boost (using a neat DCB module that kept parasitics to a minimum) followed by a PSFB running at 170kHz. I'm not sure I would do it exactly the same way now but the PSFB would certainly be considered. I have used PSFB since and also LLC but not on similar designs. The choice at this power level may well be sensibly restricted to quasi-resonant or resonant topologies solely due to managing EMI. QR and Resonant designs are very well suited to narrow input and output ranges. Battery charging needs consideration of efficiency for the whole charging cycle especially if the battery technology has a big change in terminal voltage. I think for any design there needs to be careful consideration of the cost/size/service life requirements before narrowing down on a topology - there is no panacea!

 

[treez]

Thanks, we are not sure what the exact spec is yet, its early days, but thankyou very much for your offer anyway. If we were to charge a 300-410VDC battery at 3.8kw (from 400VDC input) we would use a LLC resonant converter. We considered the PSFB but had to drop it because of the difficulty that even modern ultra fast diodes have with high trr times at the high voltages that they would see in this particular application.
But as you say, this is no panacea, because the LLC converter struggles with the load range of 300-410VDC, and in order to keep the LLC operating at f(resonant), one has to adjust the PFC output voltage over a wide range......the range of adjustment (from 440VDC downwards), is so wide, that normal PFC chips can't fully do it, and one needs to do a software controlled PFC stage.
Of course, one can just keep vin at 400vdc, use high level of magnetising current (etc), and reach the load voltage range like that, but one is not really operating very near f(resonant) at all times.....and in lighter load charging, one needs to reduce the pfc output voltage down as low as is possible to go, otherwise f(sw) gets too high.
I am sure you are familiar with all this, but its just us thinking out loud.

 

[treez]

This thread has informed us that SMPS's of a couple of kilowatts and more should not use Hard switching stages, as the noise generated by hard switching interferes with the control circuitry and causes the converter to malfunction, also that it becomes too difficult to pass EMC.
As such, how do hard switching BLDC drives of 10-20kW plus manage to function?, since they are also hard switching.

 

[treez]

-admittedly 15kW BLDC drives have lower switching frequency than general SMPS, and the transistor transition time (of the bridge IGBTs) is greater, but the IGBT DS has transitioned well within the microsecond when I used to work with 15kw BLDC drives.

 

[Easy peasy]

IGBT's are turned on slowly, and have a tail current, this reduces RFI issues...

 

[Easy peasy]

Also the control boards are usually long way from the noise sources...

 

[nrgize]

An LLC might well be the way to go these days - conduction losses were a much bigger problem 20 years ago. Mind you, I think the charger I did then had an approx 300 to 400V output voltage range - I can't remember if the control was constant current or constant power at low battery voltage. All resonant topologies (any converter to a certain extent) will suffer efficiency wise over a wide range. The LLC will work with acceptable losses quite a way off resonance if you can accept current limiting for the first stage of charging. If full power across the full range + maximum efficiency for the whole charging cycle is more important than peak efficiency, a three stage design might even be appropriate. CEC efficiency spec'?

 

[treez]

I have never seen a hard switched FB at 6kW (or anywhere near that power) running off rectified 3 mains any where near 100kHz, 30kHz at best... boost converters are far different as they process only a fraction of the thru power...

..so for example a 7kw boost converter , vin=275vdc, vout = 300 to 410vdc at 60khz, say, would be doable? (single booster, not interleaved)

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a three stage design might even be appropriate. CEC efficiency spec'?

..you mean PFC,LLC then Boost converter, then Battery load?

 

[Easy peasy]

Not only do-able, we have seen it done at 20kHz...

It is also possible to do single stage power processing at any power level, however, it is more usual to follow the conventional route, bridge rect, boost, down converter, possibly because the single stage solutions are much less explored by other engineers - stick to what you know is always a good maxim for engineers...