[LNA] What's wrong with its gain?

[yolande_yj]

The margin is enough.

Hi dsjomo. Do you have any practical design for the biasing circuit? I am thinking of the biasing scheme as the below pic from the attached paper (just bias circuit, not the gain switch method). Any suggestion?
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[Mazz]

Now it's clear what I suspected from the beginning: the LNA is stable.
Thanks for HB single point simulation: did you notice that HB sweeps is faster if you use small steps? That's because next point is calculated starting for previous one. And errors propagate...Anyway no answer from that test.
For bias circuit try with a simple current mirror biased by a PTAT current (to make gain vs. temp constant). This is a proven solution. An improvement is the selective bias: a bias that gives a low impedance at low frequencies and an high impedance at RF. This increases the LNA linearity (IP3) but the design is more complex.
If you're goint to an integrated solution, why did you match the output?
Regarding the simulation accuracy issue, the stricts settings gives you a more accurate result, and maybe the simulator error goes down. Anyway for HICUM model it seems fine.
For your receiver: why not an integrated differential solution?
I hope it can help.
Mazz

 

[dsjomo]

The margin is enough.

Hi dsjomo. Do you have any practical design for the biasing circuit? I am thinking of the biasing scheme as the below pic from the attached paper (just bias circuit, not the gain switch method). Any suggestion?
**broken link removed**

Yes I did.

But why you want this bias circuit?? This is a constant current biasing. You have to know your demand then apply the adequate solution. I read the paper, and pardon me, I think the author is not truly expert in this design issue. The most wierd thing is that the OPAMP is connected in positive feedback, but this might be INTENDED . Where you find this paper??

A constant current bias with OPAMP is usually for temperature compensation. Because gm=Ic/Vt, we have to fix gm under any possible operation temperature to keep a constant gain. But the proposed bias circuit actually lower down 1dB compression point in my thought, if the OPAMP WAS connected in negative feedback.

If the corner edge of waveform of Gain vs input power plot is very sharp, this circuit is good in 1dB performance.

 

[yolande_yj]

Now it's clear what I suspected from the beginning: the LNA is stable.
Thanks for HB single point simulation: did you notice that HB sweeps is faster if you use small steps? That's because next point is calculated starting for previous one. And errors propagate...Anyway no answer from that test.

Oh, I am very sorry for my misleading English. What I mean is that: what I get from sigle point HB simulation is very very close to what I get from the sweep HB simulation. The two plots below show the comparison. Left one is sweep HB and the right one is single point HB simulation, data is recorded and ploted in Excel.
**broken link removed** **broken link removed**

For bias circuit try with a simple current mirror biased by a PTAT current (to make gain vs. temp constant). This is a proven solution. An improvement is the selective bias: a bias that gives a low impedance at low frequencies and an high impedance at RF. This increases the LNA linearity (IP3) but the design is more complex.

I need a bias circuit consume no more than 1/10 of the LNA tail current. But a current mirror with a ratio of 1:10 causes a large discrepancy. I mean I can adjust or set an offset to the reference current to get a desired LNA main current . But is this design good? Will it change dramatically with the process varies (10 times variation)? Another concern is: when using a simple current mirror, normally we need a resistor before the base of the BJT of the LNA input port. This is to isolate the noise coming from the bias circuit. This resistor introduce more mismatch for the current mirror. Of cause I can use an LC LPF to filter out the noise, but that cost chip area. Other than that the Q of the inductor is not high. But I believe there must be a simple and practical solution for this current mirror biasing circuit, could you please advice?

If you're goint to an integrated solution, why did you match the output?

Oh, I just want to verify the LNA individually.

Regarding the simulation accuracy issue, the stricts settings gives you a more accurate result, and maybe the simulator error goes down. Anyway for HICUM model it seems fine.

I just attanded an seminar about 2 weeks ago organized by Agilent about advanced modeling. One speaker told a story about one of their customers: they use HICUM to verify a completed PA design that is done using GP model. They found that the simulation result are totally different from the GP model. Then they complain to the speaker. After investigation, they found out that it's the GP model's mistake -- the device is already broken down under that biasing condition but GP model can not predict that.

For your receiver: why not an integrated differential solution?
I hope it can help.
Mazz

I don't have this luxury for the very stringent power consumption spec.

Added after 39 minutes:

Yes I did.

But why you want this bias circuit?? This is a constant current biasing. You have to know your demand then apply the adequate solution. I read the paper, and pardon me, I think the author is not truly expert in this design issue. The most wierd thing is that the OPAMP is connected in positive feedback, but this might be INTENDED . Where you find this paper??

Hoho, you are genius. Yes, this is positive feedback. I think it is a mistake. I just search the IEEE and get it. My design concern is mention in the above reply post: current mirror mistmatch.

A constant current bias with OPAMP is usually for temperature compensation. Because gm=Ic/Vt, we have to fix gm under any possible operation temperature to keep a constant gain. But the proposed bias circuit actually lower down 1dB compression point in my thought, if the OPAMP WAS connected in negative feedback.

Lower down P1db? Why?

If the corner edge of waveform of Gain vs input power plot is very sharp, this circuit is good in 1dB performance.

Do you mean the opamp or LNA?

BTW, I am not intend to use this solution. I just want to find a simple, practical and proven biasing circuit. Any suggestion? Thanks.

 

[dsjomo]

Typically, current mirror is enough. Some ppl use 3-resistor plus a BJT to generate current or base voltage reference, this is originally for the discrete LNA module. In RFIC, most ppl use bandgap + current mirror.

Are you a student in school? Or are you a engineer??

 

[yolande_yj]

delected

 

[dsjomo]

A constant current bias with OPAMP is usually for temperature compensation. Because gm=Ic/Vt, we have to fix gm under any possible operation temperature to keep a constant gain. But the proposed bias circuit actually lower down 1dB compression point in my thought, if the OPAMP WAS connected in negative feedback.

Lower down P1db? Why?

Did you simulated this circuit in ADS? Compare this bias scheme with current mirror with large reisistive choke if you have time. Recently I'm a little busy so i can prove it on simulator.

It is just a guess according to some experience. If I'm wrong, don't blame me plz.

 

[yolande_yj]

Did you simulated this circuit in @DS? Compare this bias scheme with current mirror with large reisistive choke if you have time. Recently I'm a little busy so i can prove it on simulator.

It is just a guess according to some experience. If I'm wrong, don't blame me plz.

A large resistive choke will work for CMOS as I have done this design before. But for BJT, since it sink current, the resistor will degrade the match further. Am I right?

 

[dsjomo]

If the current ratio is 1:10, theh the resistance ratio is 10:1. So make the resistor in 10:1 ratio. As you said, this might cause mismatch. But, very small. Use a spiral with cap as choke is another choice, the penalty is higher noise figure.

Added after 3 minutes:

Did you simulated this circuit in @DS? Compare this bias scheme with current mirror with large reisistive choke if you have time. Recently I'm a little busy so i can prove it on simulator.

It is just a guess according to some experience. If I'm wrong, don't blame me plz.

A large resistive choke will work for CMOS as I have done this design before. But for BJT, since it sink current, the resistor will degrade the match further. Am I right?

Match?? Device size match or input impedance match??

 

[yolande_yj]

If the current ratio is 1:10, theh the resistance ratio is 10:1. So make the resistor in 10:1 ratio. As you said, this might cause mismatch. But, very small. Use a spiral with cap as choke is another choice, the penalty is higher noise figure.

I have tried this before (resistance ration 10:1). I need to give an offset to the reference current to make the LNA tail current correct. That means:
1. I need to depend on the accurate model of the process rather than the matching, which might be dangerous;
2. A small variation of the process, say the reference current changes ΔI, then the LNA current will change 10×ΔI. Do you think it is too much?

 

[dsjomo]

(1) You migh lost an extra transistor connected to the two base nodes. Plz see fig 3.23 in"Analog Integrated Circuit Design" Johns and Martin.

(2) The delta I always exist no matter what bias scheme you use. You should watch out the ration of (delta I / total I) instead of only delta I. In your case, (delta I / I referenc) should be roughly equal to (10*delta I / total I), and you have to make sure the 10*delta I won't damage the performance seriously.

 

[yolande_yj]

(1) You migh lost an extra transistor connected to the two base nodes. Plz see fig 3.23 in"Analog Integrated Circuit Design" Johns and Martin.

No, I have put this transistor. That's for sure.

(2) The delta I always exist no matter what bias scheme you use. You should watch out the ration of (delta I / total I) instead of only delta I. In your case, (delta I / I referenc) should be roughly equal to (10*delta I / total I), and you have to make sure the 10*delta I won't damage the performance seriously.

I need to tried this out. Thanks for your suggestion.

 

[Mazz]

Hey guys, you're going too fast!
Anyway, may I add some comments?
Current mirror with 1:10 ratio is not a very big value. The mismatch is between the two series resistors between the base of bjts can be reduced increasing their width. See you design rule manual, they should mention it.
The problem could be in the DC emitter degeneration due to parasitic inductor resistance, but it can be compensated with small resistor in the mirror diode, nothing really relevant.
Use montecarlo simulations to see it.
Regarding single end operation, be awere of this: have you design an integrated PLL with crystal oscillator?
If so take great care of the XXX harmonic of the oscillator: if it is in your RX band, with single end LNA it can be amplified in the same manner of useful signal, reducing the sensitivity. With differential design, it will be more rejected.
I hope it can help.
Mazz

 

[yolande_yj]

Hey guys, you're going too fast!
Anyway, may I add some comments?
Current mirror with 1:10 ratio is not a very big value. The mismatch is between the two series resistors between the base of bjts can be reduced increasing their width. See you design rule manual, they should mention it.
The problem could be in the DC emitter degeneration due to parasitic inductor resistance, but it can be compensated with small resistor in the mirror diode, nothing really relevant.
Use montecarlo simulations to see it.

Agree. I have tried. The matching is not bad.

Regarding single end operation, be awere of this: have you design an integrated PLL with crystal oscillator?
If so take great care of the XXX harmonic of the oscillator: if it is in your RX band, with single end LNA it can be amplified in the same manner of useful signal, reducing the sensitivity. With differential design, it will be more rejected.
I hope it can help.
Mazz

For GPS RF front-end IC, I have read some papers about that. One thing is quite interesting: for those papers writen by universities, they prefer differential LNA, while designs from companies, most of them use single ended LNA. I think for industrial, power consumption is a critical spec, we need to sacrify something.

1. 23mm2 Single-Chip 0.18pm CMOS GPS Receiver with 28mW-4.1 mm2 Radio and CPU-DSP-RAM-ROM
2. A 115-mW, 0.5-μm CMOS GPS receiver with wide dynamic-range active filters
3. A 12-mW wide dynamic range CMOS front-end for a portable GPS receiver
4. A 27mW GPS radio in 0.35um CMOS
5. A 35-mW 3.6-mm2 fully integrated 0.18um CMOS GPS radio
6. A 4-dB NF GPS receiver front-end with AGC and 2-b A/D
7. A 90nm CMOS Single-Chip GPS Receiver with 5dBm Out-of-Band IIP3 2.0dB NF
8. A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18um CMOS
9. A Fully Integrated Low-IF CMOS GPS Radio With On-Chip Analog Image Rejection
10.A fully-integrated GPS receiver front-end with 40 mW power consumption
11.An 8 mA, 3.8 dB NF, 40 dB gain CMOS front-end for GPS applications
12.Low IF Front End GPS Receiver
13.SiRFstarIIe/LP datasheet
14.SiGe Semiconductor SE4100L PointCharger GPS Receiver IC datasheet
15.NemeriX NJ1006 GPS Receiver RF Front-End IC

For the PLL VCO leakage, I want to show you a measurement result of an RF front end IC. We use a spectrum analyzer to probe at the LNA input port to measure the VCO phase noise by using the leakage signal from VCO through mixer to LNA input port. The signal level is about -45dbm. I guess this chip use sigle end LNA and single balence mixer since the reverse isolation is not good and their power consumption is very small.
**broken link removed**

 

[biff44]

Maybe you should care about the output match!

You do not define what you mean by gain, but if your "gain" is 20 log s21, then the gain is being calculated with a simulated 50 ohm load. If you have a poor output match to a 50 ohm load, you will have less overall gain. If you have a good output match to a 50 ohm load, you will have more overall gain. It does not matter if at some later time you want to hook this up to a different load. We are talking about the bump in "gain" that you showed in your plot, and we only care right now about the load that the computer software used during the simulation.

If, at -23 dBm input power, the output impedance shifts so that you have a much better match than when you have -30 dBm input power, that could explain the 3 db jump in gain.

This is just a guess, but a 3dB bump in gain is not that much, and could be a large signal impedance effect, especially if you consider a match to some harmonic generated at the higher output power.

 

[Mazz]

LO leakages not the problem that I mentioned.
In this case, -45 dBm will be amplified by LNA and converted to DC, generating DC offset, that has to be compensated.
Consider this example: PLL crystal clock 4 MHz.
394th (!!!) crystal harmonic is at 1576 MHz, so inside the RX Band, and 4 MHz is a CMOS signal.
RX overall gain= 80 dB.
An equivalent -100dBm signal (394th (!!!) crystal harmonic ) will not be rejected by lna generating an in band interferer of -20 dBm, that can decrease the sensitivity. With differential LNA you reject this signal (that is common mode one, by its nature), for about 30 dB (?) more. It means -50 dBm at output, maybe negligible.
Of course this depends on system frequencies (do not understimate also prescaler, divider otutput frequencies and their harmonics).
I hope it can help.
Mazz

 

[yolande_yj]

LO leakages not the problem that I mentioned.
In this case, -45 dBm will be amplified by LNA and converted to DC, generating DC offset, that has to be compensated.

Agree

Consider this example: PLL crystal clock 4 MHz.
394th (!!!) crystal harmonic is at 1576 MHz, so inside the RX Band, and 4 MHz is a CMOS signal.
RX overall gain= 80 dB.
An equivalent -100dBm signal (394th (!!!) crystal harmonic ) will not be rejected by lna generating an in band interferer of -20 dBm, that can decrease the sensitivity. With differential LNA you reject this signal (that is common mode one, by its nature), for about 30 dB (?) more. It means -50 dBm at output, maybe negligible.
Of course this depends on system frequencies (do not understimate also prescaler, divider otutput frequencies and their harmonics).
I hope it can help.
Mazz

Using Low-IF archetecture with a 4MHz IF bandwidth, in your example, the crystal clock is close to or smaller than the IF bandwidth. Thus the harmonic drops within the desire band. Consider a crystal clock of 16.368MHz, the IF band is from 2 to 6MHz, the IF signal is 1575.42-16.368×96=4.092. In this case, other harmonic components of the crystal clock will not down converted into the desired band because they are not less than 16.368MHz away. That means a higher crystal clock frequency will solve this problem. Am I right?

 

[Mazz]

Yes, you're right, but it was just an example.
There is a potential problem with all cmos frequencies in your IC. In my experience (not a GPS, but a receiver with more that 100 dB gain in superhet architecture) I've found output spurs coming from intermodulaton between VCO and crystal!!!!
Differentail architecture is more robust, but has to pay in current consumption. For sure.
Mazz

 

[yolande_yj]

Maybe you should care about the output match!

You do not define what you mean by gain, but if your "gain" is 20 log s21, then the gain is being calculated with a simulated 50 ohm load. If you have a poor output match to a 50 ohm load, you will have less overall gain. If you have a good output match to a 50 ohm load, you will have more overall gain. It does not matter if at some later time you want to hook this up to a different load. We are talking about the bump in "gain" that you showed in your plot, and we only care right now about the load that the computer software used during the simulation.

If, at -23 dBm input power, the output impedance shifts so that you have a much better match than when you have -30 dBm input power, that could explain the 3 db jump in gain.

This is just a guess, but a 3dB bump in gain is not that much, and could be a large signal impedance effect, especially if you consider a match to some harmonic generated at the higher output power.

I just probed the output node voltage (the node is before the matching network as shown in the pic, not the actual output port) versus the input power. Gummel Poon and HICUM models give different results.
GP model shows a abruptly increase of voltage when the input power is around -23dbm. Something must happen to the cascade transistor. Do you think it is reasonable? If yes, what happen?
BTW, how can I measure the i/o impedance when runing HB simulation?
**broken link removed** **broken link removed**

 

[Mazz]

"BTW, how can I measure the i/o impedance when runing HB simulation?"

Just follow the impedance definition: V/I.
Probe the input current and define the Zin in data display.

For output, I think you have to inject a signal on output.

I think the problem is not linked to impedance (you can check the input voltage when you sweep the power and look for some discontinuity), but on model.

Probe also the transconductance vs Pin and see if the discontinuity happens in CE or in CB transistor.

I hope it can help.
Mazz