You should submit IP design to LEGO for a prize!
correction : Power Plot is ALT+ not ^=Ctrl-click
Voltage drop is the difference between two nodes e.g. V(N001-N005)
e.g. for FET the Rs of gate and Drains with capacitance causes power dissipation.
V(N001,N005)*Id(M1)+V(N003,N005)*Ig(M1)
Here is a random design of a half-bridge driving an LC load
Note the polarity of power for L shows negative Watts for stored reactive power ( or energy per cycle) while R is +ve Pd.
View attachment 194122
I'm still trying to figure out how to organize my libraries and include references to IRF devices in LT software. (*&^%&^$%@#) while suffering from jet-lag after 2 weeks on the other side of the planet.
View attachment 194123