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help about SMPS compenstion network.

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R34 affects the overall gain, by affecting the "optocoupler" gain. The optocoupler itself has a gain of 1, but the ratio of R34 to R32 is also a gain factor.
A typical value for R34 is 2.7k. However, since all calculations have been done using 1.8k, leave it at 1.8k. You can change it to 2.7k, without too much trouble. The gain increase of 3.5dB would affect the crossover frequency only marginally. The fact that it runs at 5V has no effect, since it is the ratio of the two resistors that counts.

The voltage at pin 1 should be DC. If it is not, the P/S is oscillating or there is noise pickup. This could come from the primary side or the secondary side, coupled through the optocoupler. I can tell you how to determine where it comes from, but I am not convinced this is the problem. Try attaching pictures, they may provide clues. Don't forget, use short GND lead for the scope probe.

Traditionally, transient testing is done from 10% to 100% load. This has its roots in those converters, in which the inductors were selected to go discontinuous at 10% load. Since an inductor in DCM could create problems, the "normal" practice was to avoid that region and test in CCM ("inductor" can mean the transformer of a flyback designed to work in CCM).
By extension, the method has been used in all P/S. There are situations where testing down to 0% is necessary, but you really have to ask yourself how important this is. Is such a situation likely to occur in practice? If so, is it important that the output voltage remain within tight limits? I mean, if you simply apply voltage to a circuit, does it matter that the voltage first drops to nearly zero and then recovers? After all, just prior to that the circuit was unpowered, so this should not matter. Of course, there may be other circuits powered from the same voltage, (drawing negligible current) which may reset when the heavy load is switched in. Under these conditions, testing down to 0% is necessary.
But you can begin by testing from say 0.3 to 3A, just to see if the behavior is different. Perhaps we can draw some conclusions from that.

Basically, the transient response means just the output voltage. Look at the picture. This is what the output voltage should look like on a well-behaved P/S. The difference between the inner horizontal dashed lines represents the effect of the load regulation. The difference between the peak or valley and the flats represents the transient response. Usually, this should be less than 4-5% of the output. Measure also the recovery time. Typical values are from a few hundred µs to about 1ms.
Usually, the transient response is measured with the scope set to AC, and the sensitivity set in such a way as to allow easy measurement of the waveform characteristics. The load switching frequency must be low enough for you to observe the flat portions, i.e. low enough to allow the P/S to recover after the transient.
 

ok so i removed that foldback and set it up like you had mentioned. It seems that it runs at 140kz all the time which is great because thats what it should do. Still have a problem with a no load to lets say one amp load. The output votlage dips sometimes to about 5 votls before recovering back to 12. So i am all entirly sure that the frequency foldback was playing a role in the problem with the output not maintaing regulation during a transient.
So i ask you what wave forms would you like so that you could give me some insight because right now i am fresh out of ideas! I have a ciruit board setup with the frequency foldback and without the frequency foldback so just let me know what wave forms you would like to see!
Thanks for all your help!
 

On the board without the frequency foldback, can you just do a plot of the output voltage transient, for say a 0.5A to 1A change first, just like I described in the previous post? That is, the scope AC coupled, and the transient frequency low enough?
Then you can do it for 0 to 3A and attach pictures of both.
 

ok here are two pictures i saw
by the way the problems of transients are gone at high input voltages with the frequency foldback removed and the circuit hooked up as you advised!
the circuit still outputs 12 volts at 3 amps with no problem running at 140kHz
i am surpirise the circuit works i was thinking that i would have problems sinking the currnt through the mosfet with such a small on time due to the high inoput voltage
i think i am going to plan to leave out the freq foldback since the circuit seems to done fine without it! let me know what you think and if you want more pictures to observe

first picture is input vac of 100V and a 0 to 3A transient
channel 1 is the output votlage ac coupled
channel 2 is the control voltage at pin 1 dc coupled

second picture is input vac of 300 and 0 to 3A transient
channel 1 and 2 are same as last photo
 

The pictures do not look encouraging at all. The output voltage dips about 10V!
What is the actual time/div? Is it really 25ms in one picture and 5ms in the other?

Clearly, the problem is that the voltage at pin 1 is very slow to react. It should rise immediately as the output voltage begins to drop, but it takes a long time for it to do so. Are you sure you removed all the large caps from the error amplifier compensation? I simply cannot believe that the 390pF/3.9nF caps are causing such a delay. It seems to me the time base is 5ms/div, so it takes about 7ms for the voltage at pin 1 to rise. But 130k*3.9nF=0.5ms. That does not make any sense.
Therefore, can you please check with the scope the voltage at pin 8 of the chip? Yes, that is Vref. It might be possible that the chip actually shuts down during the transient and then restarts. The reference voltage should obviously be DC, with NO trace of a dip when the transient happens.
If you find that the voltage at pin 8 actually dips, then I think you should increase cap C23. I always thought it was too small. Typical values are 47-100uF. Of course, that will have an effect on the start-up time, but I think you can tolerate that.
Come to think of it, why did you use the UC3845? Normally, for AC/DC, one would use the UC3842/4, which have a wider hysteresis on the shutdown circuit. The UC3843/5 are typically used for DC/DC converters.

In the first picure, it seems that there is some kind of "oscillation" on pin 1, which I cannot explain. It does not seem a real oscillation, but rather it seems caused by something drawing current at that rate from the output, as the pulses are visible on the yellow trace, too. What was used to create the transients? Was the signal clean?

What do you mean that the transients are fine if the frequency foldback is removed? Aren't these pictures taken with that removed?

The fact that the circuit works at 140kHz and 600V is no surprise to me. But running it at high frequency and high voltage will cause higher dissipation in the MOSFET. That is why it was there in the first place. I think that frequency foldback is a good idea, but I recommend you implement it in a fashion similar to the appnote I suggested at one point. Basically, just use a divider off the input DC voltage and use that to turn on a transistor that will "steal" some current from the oscillator's charging current, resulting in a lower frequency. The circuit can switch the frequency abruptly, say at about 300VAC. The limits should still be 140 and 70kHz. That will ensure lower MOSFET dissipation at high voltages, while still allowing you to use the (small) transformer you currently have.
 

ok first thing! nice job! i looked at the vref pin and its waveform is like a pulse every so ms so when it pluses thats when the control voltage kicks in and starts to regulate which explains why when i sometimes would go from 0 to 3 amp load the transient woult not be seen vs sometimes i would see a huge dip until that pulse came along and brought the control voltage to where it needed to be. So why is it pulsing at vref i have no idea but i am about to go up the capacitance for the Aux winding so hopefully that solves our problems. ill also get you a waveform so that you can see what i mean about pulse!

once again i really apperciate your time and your eagerness to help me!

Added after 30 minutes:

ok i changed the 10uF cap to a 47uF cap and the Vref line is a dc signal once again! YAH
but wait i got up to about 500VAC and the vref started to turn into pulses again! So one thing is i should get frequency foldback because it cannot sink enough current cause the gate is on for such a short time , or i can increase that cap to 100uf. Which one would you suggest. Also i think i am going to have a tech changed one of my boards back to having frequency foldback via the 3.3V zener but beef of the capacitor to 100uF and see if that solves my problems.
Let me know what you think. ill try to get some waveforms for you

Added after 13 minutes:

another minor detail i would also like to fix up is
now at low input voltages with like 100-120 vac and output at full load 3A the output voltage sags a little like say to 11 V
this ony happens below 120 vac and at full load.

Added after 28 minutes:

one more thing!! i just blew the mosfet out due to heat. so do you have an recomendations for an article or book on calculating heat sink junction temp and all that so i can choose a suitable heatsink for this application. I also am going to make C23 100uF just because at high line vref was sagging past 500VAC for some odd reason!

I apperciate all your help and when i have the techs replace some parts ill get some pictures!

I also today used an LC filter on the output. I used 220uF and 7.22uH for a doble filter pole at roughfly 4kHz. Is this suitable for the application and is there a really in depth way of calculting a LC filter or is it just pick and choose hwere you want it. Also i was wondering if ther eis a book or article for LC filters on power supplies. Let me know i enjoy al the reading material that i can get my hands on!

If there are any waveforms you would like to see in particular let me know thanks!

Added after 1 hours 17 minutes:

i want to make sure i calculate the output ripple current correctly also so i do not kill my output capactor. Right now i have 1.5A amp ripple rating on my capacitors does that seem doable for 3A flyback
thanks
 

It is best to increase the cap to 100uF. Also, it would be a good idea to use a UC3844, since the hysteresis is wider so it will take a lot more voltage dip on that cap for the chip to shut down. Vref pulses because the chip shuts down, which happens when the supply voltage (pin7) drops below a threshold.
Since you are so close to shutdown, perhaps it would be a good idea to add another turn to the transformer's ausiliary output, in order to increase the normal operating voltage. That will allow you more headroom. But be careful, do not increase that voltage too much, 12-13V should be OK. More than that will cause too much dissipation in the chip.

Please try to implement frequency foldback the way I suggested. It should not be that hard. But perhaps you should first try to solve the shutdown question, before attempting anything else.

The heatsink "calculation" is nothing more than calculating the losses in your MOSFET and dividing that power by the sum of the thermal resistances: junction to case (for a TO-220 about 1~1.5°C/W), plus the thermal resistance of the insulator material if any (mica, or silicon rubber, or whatever; for these, thigs are more complicated, but about 2~3°C/W is typical for a TO-220, unless you use alumina, in which case it will be about 0.3~0.5°C/W), plus the thermal resistance of the heatsink, which is available from the catalog.
In the end, at the maximum operating temperature, you should ensure that the junction temperature is not higher than 100~110°C.

For example, assume the MOSFET dissipates 5W worst-case. The thermal resistance from junction to case is 1°C/W, the insulator has 3°C/W and the maximum ambient is 50°C. Maximum allowed junction temp is 100°C.

The maximum allowable thermal resistance from junction to ambient is then:
Rthja=(100-50°C)/5W=10°C/W.
Then the thermal resistance of the heatsink is simply:
Rthhsk=10°C/W-4°C/W=6°C/W.
(Since you already have 4°C/W for the junction and the insulator)
Select a heatsink with that thermal resistance at the given airflow (no airflow if convection-cooled).

The LC filter is calculated basically as you did, but quite often you just select sopmething that works, or is used in another design already, or is easily available, etc. I do not know if there is a special book about LC filters.

I have posted some formulas for cap RMS current calculation. Use them and see where you are. But I think you will find it's in the 5~6A range, so you should parallel maybe 3~4 caps at the output. And remember that they have to be derated for RMS current, too. To about 70% of the rating.
 

i am having trouble realizing the frequency foldback circuit.
i am thinking i should use a voltage from the 82k chain.
so at high voltage 600 volts should hhave 850 on the rail
so first 82k reisitor off of the line should have about (850-12)/5 +12 volts on it. i was thinking of sensing there and using a resistor divider to ground off of that. i was thinking i probally need to use an NPN in this case. What kind of didoe shoudli use? i was thinking of a fast signal diode like the one useded above the cap on the uc3845
just i am confused on how to turn the NPN at the right time without drwaing huge amounts of current ie vbe whould be above .7 thus increasing cuurent

i posted a pdf of something i thinmk might work. i messed up though and i think R6 should be 7.3K! Also i was wondering what kinda of NPN and diode would be siutable for this application. Give me a pointer or two if you think this circuit will not work! I could also sense of of the lowest bleeder resistor if i wanted?


I have posted some formulas for cap RMS current calculation. Use them and see where you are. But I think you will find it's in the 5~6A range, so you should parallel maybe 3~4 caps at the output. And remember that they have to be derated for RMS current, too. To about 70% of the rating.
i was looking and as you decrease the value lets say to 3 *330 uF the ripprle ratting per capactior decreases so when you have 3 of them its the same as having 1 1000uF capactior so how do you get enought for 5 to six amps because to me that does not even seem feasible. Plus i do not think other power supplts put that much on the ouytput!!
 

The transistor you selected is OK. Instead of a diode, use a resistor. You do not want to stop the oscillator completely, just to decrease its frequency. Calculating that resistor is not so easy, I think experimentation is the easiest way. The power supply does not have to be running for this. In fact, it should not be running, just in case you get too low a frequency. Just disconnect the MOSFET and test the chip's oscillator only. In fact, you do not need the transistor to start, just connect resistors (hundreds of kohm) in parallel with the oscillator capacitor, until the frequency reaches 70kHz. That will be the resistor.

As for the divider, you did the right thing. However, you may need to move the 1M resistor top connection to the point above R4. The threshold at which the transition happens will have to be adjusted from the 1M/3.9k resistors. I realize this whole circuit may be a tricky thing to adjustm but if you cannot afford a second divider, you will have to play with what you have already on the board. The transistor will not need a lot of base current, since the collector current is also low. The 3.9k resistor can be probably much larger, say 39kohm or more, to avoid a large current through it at 0.7V. If you think noise will be a problem you can put a cap across it.

The capacitors I meant were 3900uF, not 330uF. You will need probably 3~4 of them in parallel. Just do the RMS current calculation and see how much current you actually need. Divide that by 0.7 and you get the cap rating. If you cannot find a single cap that has that rating, use more in parallel until you reach that current level. I don't know what power supplies you looked at that were using fewer capacitors, but you should make sure they were discontinuous flybacks, outputting 3A of current, for a fair comparison.
Anyway, do the calculation based on the actual measured diode on-time and frequency and see exactly where you are. This is the safest way, knowing what really is there.
 

correct me if i am wrong but i choose 3.9K so that the transistor turns on at right time mainly 300VAC
if i am incorrectly choosing theses values let me know how i should choose them.

secondly i only calulated 1AMP RMS cap current for worse case so i am not sure how you came about the 5 to 6amps cause you were really getting me worried.
 

The 3.9k will draw about 150uA . That means your divider will have to supply this current all the time and it will affect the startup time. If you are OK with everything, keep it that way.

I will have to review the RMS current, when I get home, I am on my way out now.
 

Assuming the diode conduction time is 0.48*Tsw, then the diode peak current should be:
Ipk=2*Iout/0.48=12.5A

Then the RMS current in the diode is
Idrms=Ipk*sqrt(0.48/3)=5A

And the cap RMS current is
Icrms=sqrt(Idrms^2-Iout^2)=4A


If the diode conduction time is about 0.3Tsw, as I recall it was in your pictures, then the values become:

Ipk=2*3/0.3=20A
Idrms=20*sqrt(0.3/3)=6.32A
Icrms=sqrt(39.94-9)=5.56A
 

ok i was talking to someone who has lots of power supply experience and he mentioned that i should also have an rcd snubber from drain to ground. I have read though that you should choose one and not have both because they just wasted of parts and space.

What do you think i should have?

If you have any articles on them please let me know i would like to read as much as possible about RCD snubbers.
 

The "snubber" you are talking about was used in the days of the bipolar transistors, and back then you did indeed have two RC(D) circuits. One of them was really the RCD snubber returned to the supply rail, whose function was, as is on the MOSFET, of limiting the leakage inductance spike.

The second one, to GND, was actually intended to slow down the rise of voltage across the transistor, because the bipolars exhibit the secondary breakdown phenomenon. That, however, is not the case with MOSFETs, which are able to tolerate the full rated Vds and the full rated Id simultaneously.
Hence, the only RCD snubber you see in a P/S using MOSFETs is the RCD snubber meant to limit the leakage spike.

You may find this appnote helpful https://www.onsemi.com/pub/Collateral/AN1680-D.PDF
 

thanks for the app note! it was very insightful!
Right now i am having a ton of trouble locating capacitors to do the job while meeting requirments. I found that i can use 3 680uF caps with 25V rating and 1.8Vrms rating to meet the spec.
The caps are radial though

basically i am havin trouble locating a combination of capactiors that will meet the unreal high capacitor ripple of 6 amps while keeping cost and board size low.
any help?

what if i only design for 3 amp ripple will the caps just have a very short life?

right now in the circuit i have 1000uF with 1.5A rating. Will this capacitor just die soon?
 

The caps will indeed die, especially at higher temperature.
Did you run the P/S for, say 1/2 hr or 1hr at max load? You should then touch the caps and see how hot they get. Usually, their temperature should not increase by more than 10C over the ambient.
 

Hi there.
I read through most of this thread now. Just wanted you to know that my work has been successfully using the design ideas from Mary Brown's wide input design for a few years now (5V output only)
The project I'm just starting is re-factoring it to make it more efficient, different form factor, updated components, etc. So I'm tryng to get a better understanding of how it works...
It looks like the way we got the variable frequency control to work was by adding in a 12V regulator from the AUX winding (nominally 20V) to stabilize and filter the RTCT reference supply.

Also, for the output filter caps, we're using 4 of these guys:
**broken link removed**
or
**broken link removed**
And we also have an additional L+C at the output

PS. Just wondering if you know where the 7.7V value comes from in computing Rt on page 9 of AN1327/D?
 

VVV i was wondering if you are still around. I am looking for some advice on power supply layout. We have a problem and we are not passing EMI conducted or emissions testing. I know the basics like keep the power switching loop as short as possible but is there a book or hints i can have for layout of a switching power supply so that i can pass EMI. I think i also have to lower my 3db on my line filter if i am not passing conducted as well. Any thoughts or suggestions would greatly be appreciated.
Thanks
 

Generally all the books will tell you about the same thing: keep this and that short.
You probably know this yourself.
There is one book out there, that I am aware of and it contains some good info:
Swithcmode Power Supply Design by Keith Billings.
I am certain there are others, but this is the one I know.

Anyway, if you want, you can send me the layout and I can take a look; maybe something will jump at me as being totally wrong.
 

i did not pass first round of EMI testing so i have some questions.
since my primary GND is floating do i need to tie it to Chasis GND somehow?
Do i also have to tie my secondary GND to chasis. The secondary gnd is the gnd on the DC of the flyback.
I have a chasis gnd connected to my heatsink and to the input line PI filter.

Any help on this would greatly be apperciated.
Thanks again!
 

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