Assuring stability with Voltage Mode TOPswitch Flybacks?

[cupoftea]

Hi,
We are trying to use TOPswitch HX and JX flyback control chips , but with transformers with NP/NS's
which mean that our design is not supported by their PI Expert Suite software.
Please help us to use TOPswitch's in such use case?

As such, we need to be able to calculate the gain and phase margin of our TOPswitch designs. However, we cannot do
this since TOPswitch modulator gains are the secret IP of Power Integrations.
And since the PI Expert Suite software cannot be used with our transformer's, we cannot assure stability
of our designs. This is bad because voltage mode converters offer additional problems with stability and so
must be done with a feedback loop calculation.

The TOPswitch is a voltage mode controlled chip (certainly when on or near max power).

Transient response testing is not sufficient to prove good stability margins with
voltage mode converters like TOPswitch….as the following article by Dr Ray Ridley discusses...

Transient response & Loop gains of power supplies (Dr Ray Ridley)

_17 Transient Response _STEP response n stability.pdf

drive.google.com

..with a current mode SMPS, you can get better gain and phase margins by simply lowering the loop
bandwidth.....but this is not so for voltage mode converters. As the above discusses.

So we then need to calculate the gain and phase margins. -But this isn't possible with TOPswitch, since
the modulator gains inside the TOPswitch are kept secret.

So in summary, for a voltage mode converter, one must calculate out the gain and phase margins....ie, you have to make out
the Bode Plots.....you dont necessarily have to do this with current mode converters......Dr Mike Engelhardt emphasis this in 1:55 to 2:30
of his video as follows...

QuickStart Guide for QSPICE® Simulation Tool

This video provides a comprehensive introduction to QSPICE.

www.qorvo.com

...But how do we calc the Bode plots for a TOPswitch when Power integrations keeps the internal modulator gain a secret?
The modulator gain is needed to be known to calc out the Bode plot.

In the following communication, Power Integrations applications engineers actually state that the
feedback loop parameters of the TOPswitch internals are the secret IP of Power
Integrations and so are not divulged to the public. Therefore, without the modulator gain of the TOPswitch
we are simply unable to do the feedback loop calculation for the TOPswitch..

Bode plots for TOPswitch HX Flyback

Hi,

www.power.com

Page 47 of "power supply design, volume 1:control" by Dr Ridley states that for a voltage mode flyback.."The crossover frequency should be at least twice the resonant frequency".......by "resonant frequency" , Dr Ridley means resonance of Cout and L(sec). [or rather "LE", the effective secondary inductance since its flyback and not full or half bridge).

Also, Basso states that Voltage Mode Flyback crossover should be three times less than the RHPZ frequency (our designs go into
CCM at low mains and so RHPZ becomes an issue)
….the above two facts mean that there is only a narrow band of possibilities for the crossover frequency of a voltage mode flyback like TOpswitch. A little variance in the tolerance of the opto, or whatever, and the whole thing could go unstable. Not only that,
but TOPswitch designs often use a NPN in the feedback loop. NPN's have very poor tolerance, and so the chances of running into
stability at some point with a TOPswitch design is quite high.

Page 25 of AN-47 shows the NPN being used in the topswitch feedback loop....

AN-47

https://www.power.com/sites/default/files/documents/an47.pdf

Incidentally AN57 does not refer to TOPswitch HX or JX as the following tells....

Bode plots for TOPswitch HX Flyback

Hi,

www.power.com

Page 4 of AN57 by power integrations suggests that the LC resonant frequency of a TOPswitch flyback
should be greater than 500Hz...

AN57

https://www.power.com/sites/default/files/documents/an57.pdf?download=1

This imposes a tight limit on the TOPswitch output capacitance, and throws into peril any output loading which may also feature an extra , large
electrolytic capacitor....instability may well then ensue.

Do you know what lies behind this recommendation of LC resonant frequency >500Hz?
Is it the fact that with TL431 based compensators that feature the "fast-lane/slow-lane" paths, the Type 3 compensator
is especially poor when LC resonance is >500Hz?

Here's a bit more on the TOPswitch Flyback output LC resonance frequency being >500Hz...

Voltage mode CCM flyback has limitations on output capacitance - Page 1

Voltage mode CCM flyback has limitations on output capacitance - Page 1

www.eevblog.com

I mean, supposing your TOPswitch flyback suffers high variance in the opto CTR because you have five different parts as being "OK" in the BOM and need that flexibility to keep costs and lead times down....Or suppose the ESR (or the capacitance itself) of your output caps is highly variable.....or supposing some customers connect loads which comprise additional electro caps, thus dramatically increasing the output capacitance...etc etc.......current mode controllers can shrug this off and stay stable...a voltage mode converter may well go totally unstable under such changeable conditions.....

Like was sais, if the TOPswitch design is from the PIXIS design suite, or from the PI Expert software, then your good.....but if not......then surely one is in danger of instability?

 

[Easy peasy]

I am not that surprised by the above, except that:

Power Integrations engineers also declare it as Voltage mode control.

is obviously a reference to closing the volt loop using the comp pin - nowhere do they say it is solely volt mode - which if some of the commenters on here had ever tried to build a CCM flyback under volt mode only - would realise their folly very quickly into the process - esp at light loads.

This is also why the ToP switch is limited in the lowest pri inductance it can switch, due to the leading edge blanking and steepness of current rise - factors that do not occur in pure volt mode.

also, nowhere does it state this: " Voltage Mode control when in "full frequency PWM mode" " they actually say pwm - which hides the operation nicely

the internal current mode loop exists nicely inside the ToP switch - with no fiddling needed by newbies - they have largely taken care of the volt loop with their current method and large cap on the comp pin - meaning anyone can close the loop and at worst case get a slow response - and at best case get a loop fast enough that only an internal peak current mode system can actually supply. QED.

 

[cupoftea]

which if some of the commenters on here had ever tried to build a CCM flyback under volt mode only - would realise their folly very quickly into the process - esp at light loads.

Thanks, The PI engineers on their PI forum say its voltage mode when peak current is above 55% of imax.
Also i think we are talking at cross purposes again, because yes, it is not in Voltage Mode control at light load. (ie, when ipeak is at or less than 55% of imax)

The datasheet description nowhere depicts a peak current being taken to a PWM comparator along with the error amplifier signal.

The entire chapter 8 of Dr Basso's book is referring to it as Voltage Mode Control.....are you saying that Basso's entire 8th chapter of this book is wrong?

Amazon.co.uk

Dr Basso must have had permission from Power Integrations to write that. Dr Basso is one of the foremost SMPS control engineers in the world today.
According to you his entire 8th chapter is full of serious errors. ie mistaking Current Mode control for Voltage Mode Control.

Also, if its current mode then one would need to know the current sense resistors value , as its a needed feedback loop parameter.

I suspect that anybody can say anything no matter how outrageous about TOPswitch now and get away with it, because the Innoswitch appears to be the all encompassing part of Power Integrations now....at least regarding offline flybacks. Many TOPswitchs are now obselete or "not recomended for new designs".

This is also why the ToP switch is limited in the lowest pri inductance it can switch, due to the leading edge blanking and steepness of current rise - factors that do not occur in pure volt mode.

Thanks but its only in voltage mode when ipeak is >55% of imax.

 

[Easy peasy]

Ha ha, I got an advance draft of that book from M. Basso to check - but I was overseas and failed to do any reading before it was handed to the publishers



There is no where that PI explicitly states that it is in volt loop only above 55% of I max - reading comprehension again.

Also - you can use the ToPswitch as a UPF boost switcher - this would not be possible at all without current mode throughout - with a slow closing volt loop for the 385-420 VDC out.

https://u.dianyuan.com/bbs/u/18/1086229328.pdf

and further please note:

you would never get close to 1kHz loop closure freq ( never mind 3kHz ) without an internal current loop - but only a learned mind would appreciate this fact. You'd be lucky to get 100Hz and be stable at no load.

QED.

 

[cupoftea]

There is no where that PI explicitly states that it is in volt loop only above 55% of I max

Thanks but There is nowhere that it says its in Current mode when above 55% of imax either.
Its obvious from the explanation on page 9 of TOP-HX datasheet that its volt mode above 55% of imax.

Also - you can use the ToPswitch as a UPF boost switcher - this would not be possible at all without current mode throughout - with a slow closing volt loop for the 385-420 VDC out.

Thanks but Voltage Mode is common in PFC boost controllers...take the LT1248 where you clearly see the artifical ramp into the PWM comparator...on page 11 block diag....
LT1248

https://www.analog.com/media/en/technical-documentation/data-sheets/1248fd.pdf

Also, i suspect the equation 8.35 (attached) which depicts a type 3 transfer function for the TOPswitch/TL431/Opto configuration. The numerator shows "1+wz2/s", but a zero is of the form "1+s/wz2".

 

[Easy peasy]

aaah, geez, the LT1248 uses ave current mode - where the slope comp is effectively built in to the Cea - otherwise it wouldn't work - at all.

it looks at the current and the rectified Vac in:

it's a copy of the UC3854.

It's a pity Basso didn't ask PI for full detail - closing a fast volt loop requires a fast internal current loop - else it don't work

the proof as always is in the pudding - try closing a volt only loop at 1kHz on LTspice, just in CCM at full power - you'll see . . . oh yeah - then do a load step from 60 - 100 % and back and see where your volt loop only gets you . . .

 

[cupoftea]

from your page 9, what is described is a round about way of describing peak current mode - which you are apparently unable to spot,

Thanks, but lets look at the Hiper-TFS, a 2 Tran Forward chip by Power Integrations.

https://www.power.com/sites/default/files/documents/hipertfs-2_family_datasheet.pdf

Its feedback is analogous to that of the TOPswitch...except for Hiper-TFS it looks at the current being drawn out of the FB pin by the opto...and then assigns a duty cycle depending on that......whereas TOPswitch it looks at the 'excess' current being supplied into the CONTROL pin by the opto.

Hiper-TFS is definitely voltage mode......and so too is TOPswitch.
The basics of the operation of the Hiper-TFS are essentially the same as the TOPswitch with regard to duty cycle setting, and both are in Voltage Mode Control when at Max Power.

I am pretty sure Power Integrations dont do any Frequency compensated chips which are current mode control when at max power. (dont know about innoswitch as it doesnt say, and the user doesnt do any frequency compensation for that anyway).

how unlikely is it that PI would drop out of pk current mode at near full power - very unlikely - the gain change and the double pole would quickly lead to oscillation for solely volt mode

Thanks, but Hiper-TFS is voltage mode...and they just get people to compensate it for voltage mode...ditto the TOPswitch.

It's a pity Basso didn't ask PI for full detail - closing a fast volt loop requires a fast internal current loop - else it don't work

Thanks, but what about Hiper-TFS? , which they state is Voltage Mode Controlled. Are you saying that doesnt work too?
I appreciate the Hiper-TFS has no RHPZ, but with TOPswitch flybacks, they are arranged so that the RHPZ is pushed out to high frequency.

aaah, geez, the LT1248 uses ave current mode -

Thanks, i appreciate its called "average current mode"...but its a Current Error amplifier output feeding into a PWM comparator, along with an artifical ramp, and is effectively Voltage Mode Control as such....as you know, it does not "look" at the instantaneous peak current as in Current Mode Control. The LT1248 is effectively "voltage mode control applied to the current error amplifier output instead of to the voltage error amplifier output."

--- Updated Today at 5:39 AM ---

___________________________________________----
___________________________________________----
Well, If the TOPswitch is not in Voltage Mode then its very strange, because
the Bode Plot calculations which consider it as voltage mode, come out very identical to the
actual Bode plots given in the DER243 application note. (and the ones in DER243 are from
the lab with use of a gain phase analyser.)
(excel as attached)

However, I had to use Basso's equation for the TOPswitch/TL431/Opto transfer function.
(on page 467 of his book "Designing control loops......")

Also, I had to use Basso's Voltage Mode CCM Power stage transfer function as in page 231 of his book "SMPS".
But I had to switch the gain factor from that shown in the "SMPS" book to the one given in AN57 equation 11.
This had to be done as Power Integrations don't give the ramp peak voltage for TOPswitch.
(However, if i had taken the ramp peak as 1Volt, then i could have just used Basso's equation 2A-18 in its whole-some form
as that would have been the same as the AN57 supplied gain.)

So if TOPswitch is not in voltage mode, then how has the attached come out as very identical to the
DER243 supplied Bode Plots.?

DER243

https://www.power.com/sites/default/files/documents/der243.pdf

 

[Easy peasy]

Hiper-TFS is voltage mode

No it ain't - and it does not say so in plain english anywhere I can see.

closing the external volt loop - yes - easy & pleasant, knowing the high performance requires an inner current loop - priceless,

again, why would PI go to all the trouble of using the internal fet to provide a temperature compensated I sig - and then not use it for best performance ?

again, all the proof needed is to try closing a loop at 1kHz in LT spice for an 100 watt flyback - that is just in CCM at full power - and load stepping - using volt mode only - suddenly you're down to sub 100Hz and a type 4 compensator to have stability at light loads.

QED.

 

[mtwieg]

is obviously a reference to closing the volt loop using the comp pin

This is not obvious at all.

nowhere do they say it is solely volt mode

Neither does it ever mention current mode.

which if some of the commenters on here had ever tried to build a CCM flyback under volt mode only - would realise their folly very quickly into the process - esp at light loads.

This is also why the ToP switch is limited in the lowest pri inductance it can switch, due to the leading edge blanking and steepness of current rise - factors that do not occur in pure volt mode.

Your case seems to be based not on any information from power integrations, but rather your own intuition as an engineer. Understandable, often we have to fill in the gaps with our best judgement.

My own intuition doesn't see any issue with voltage-mode control so long as one is willing to accept a very low crossover frequency (I consider ~1KHz to be super low). Ultimately crossover frequency is going to be restricted by the RHPZ regardless of whether CMC is used or not. Voltage mode imposes a little extra penalty, but likely not an issue if you're already willing to accept such a low fc.

But consider AN-57 (which the OP also mentioned), which explicitly states several times that TOPSwitch parts are voltage mode, including transfer function plots showing the classic second order response. Nowhere does it mention current mode control or anything similar to it. It's unclear if this document actually applies to all TOPSwitch families; the only specific families I can see referenced are GX and JX. The JX series, at least, also has contradictory plots showing peak drain current and duty cycle being directly dependent on control current.

 

[cupoftea]

No it ain't - and it does not say so in plain english anywhere I can see.

Thanks, but yes it does...page 17, top of left hand side text under "Feedback Loop Design"
(the hiphen makes it not show up on 'Control-F' type document searches)
Page 3 (RHS at about centre of page) also declares it as Voltage Mode Control.

Hiper TFS datasheet (Voltage Mode 2 tran forward controller)

https://www.power.com/sites/default/files/documents/hipertfs-2_family_datasheet.pdf

...So are you now going to say that Hiper-TFS cannot be made to work in a worthwhile way due to its use of Voltage Mode?

My own intuition doesn't see any issue with voltage-mode control so long as one is willing to accept a very low crossover frequency (I consider ~1KHz to be super low). Ultimately crossover frequency is going to be restricted by the RHPZ regardless of whether CMC is used or not. Voltage mode imposes a little extra penalty, but likely not an issue if you're already willing to accept such a low fc.

Thanks, good point, though again it depends what your "low" means...the TOPswitch Flyback in DER243 has a crossover frequency of 4.6kHz and its in CCM, Voltage Mode for that. The RHPZ is at 143kHz for this. The Power stage double pole is at 1060 Hz.
So the Voltage Mode, CCM , TOPswitch flyback of DER243 is crossing over more than 3x above the output double pole frequency....as you know, something that would be considered acceptable for Voltage Mode with a Type 3 compensator (which they use).

suddenly you're down to sub 100Hz and a type 4 compensator to have stability at light loads.

Thanks, but again we are talking at crossed purposes....The TOPswitch is no longer in Voltage Mode when in light load (ipk less than 55% of imax)

________________----______________
Fig 16, page 17 of the Hiper-TFS datasheet is interesting though.
The text below fig16 says that R21 and C8 provide a zero near the LC
double pole location. This is not correct. To make R21 and C8 form a zero,
the supply through the opto diode must be by way of a voltage regulator.
This is clearly demonstrated in Basso's Book "Designing control....." on pages 424 to 429

 

[cupoftea]

Please note..
Page 8 (2nd paragraph down) of the below declares that TOPswitch in in Voltage Mode Control
whenever ipk is >55% of imax..

DER188

https://www.power.com/sites/default/files/documents/der188.pdf