Assuring stability with Voltage Mode TOPswitch Flybacks?

[cupoftea]

Hi,
We are trying to use TOPswitch HX and JX flyback control chips , but with transformers with NP/NS's
which mean that our design is not supported by their PI Expert Suite software.
Please help us to use TOPswitch's in such use case?

As such, we need to be able to calculate the gain and phase margin of our TOPswitch designs. However, we cannot do
this since TOPswitch modulator gains are the secret IP of Power Integrations.
And since the PI Expert Suite software cannot be used with our transformer's, we cannot assure stability
of our designs. This is bad because voltage mode converters offer additional problems with stability and so
must be done with a feedback loop calculation.

The TOPswitch is a voltage mode controlled chip (certainly when on or near max power).

Transient response testing is not sufficient to prove good stability margins with
voltage mode converters like TOPswitch….as the following article by Dr Ray Ridley discusses...

Transient response & Loop gains of power supplies (Dr Ray Ridley)

_17 Transient Response _STEP response n stability.pdf

drive.google.com

..with a current mode SMPS, you can get better gain and phase margins by simply lowering the loop
bandwidth.....but this is not so for voltage mode converters. As the above discusses.

So we then need to calculate the gain and phase margins. -But this isn't possible with TOPswitch, since
the modulator gains inside the TOPswitch are kept secret.

So in summary, for a voltage mode converter, one must calculate out the gain and phase margins....ie, you have to make out
the Bode Plots.....you dont necessarily have to do this with current mode converters......Dr Mike Engelhardt emphasis this in 1:55 to 2:30
of his video as follows...

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...But how do we calc the Bode plots for a TOPswitch when Power integrations keeps the internal modulator gain a secret?
The modulator gain is needed to be known to calc out the Bode plot.

In the following communication, Power Integrations applications engineers actually state that the
feedback loop parameters of the TOPswitch internals are the secret IP of Power
Integrations and so are not divulged to the public. Therefore, without the modulator gain of the TOPswitch
we are simply unable to do the feedback loop calculation for the TOPswitch..

Bode plots for TOPswitch HX Flyback

Hi,

www.power.com

Page 47 of "power supply design, volume 1:control" by Dr Ridley states that for a voltage mode flyback.."The crossover frequency should be at least twice the resonant frequency".......by "resonant frequency" , Dr Ridley means resonance of Cout and L(sec). [or rather "LE", the effective secondary inductance since its flyback and not full or half bridge).

Also, Basso states that Voltage Mode Flyback crossover should be three times less than the RHPZ frequency (our designs go into
CCM at low mains and so RHPZ becomes an issue)
….the above two facts mean that there is only a narrow band of possibilities for the crossover frequency of a voltage mode flyback like TOpswitch. A little variance in the tolerance of the opto, or whatever, and the whole thing could go unstable. Not only that,
but TOPswitch designs often use a NPN in the feedback loop. NPN's have very poor tolerance, and so the chances of running into
stability at some point with a TOPswitch design is quite high.

Page 25 of AN-47 shows the NPN being used in the topswitch feedback loop....

AN-47

https://www.power.com/sites/default/files/documents/an47.pdf

Incidentally AN57 does not refer to TOPswitch HX or JX as the following tells....

Bode plots for TOPswitch HX Flyback

Hi,

www.power.com

Page 4 of AN57 by power integrations suggests that the LC resonant frequency of a TOPswitch flyback
should be greater than 500Hz...

AN57

https://www.power.com/sites/default/files/documents/an57.pdf?download=1

This imposes a tight limit on the TOPswitch output capacitance, and throws into peril any output loading which may also feature an extra , large
electrolytic capacitor....instability may well then ensue.

Do you know what lies behind this recommendation of LC resonant frequency >500Hz?
Is it the fact that with TL431 based compensators that feature the "fast-lane/slow-lane" paths, the Type 3 compensator
is especially poor when LC resonance is >500Hz?

Here's a bit more on the TOPswitch Flyback output LC resonance frequency being >500Hz...

Voltage mode CCM flyback has limitations on output capacitance - Page 1

Voltage mode CCM flyback has limitations on output capacitance - Page 1

www.eevblog.com

I mean, supposing your TOPswitch flyback suffers high variance in the opto CTR because you have five different parts as being "OK" in the BOM and need that flexibility to keep costs and lead times down....Or suppose the ESR (or the capacitance itself) of your output caps is highly variable.....or supposing some customers connect loads which comprise additional electro caps, thus dramatically increasing the output capacitance...etc etc.......current mode controllers can shrug this off and stay stable...a voltage mode converter may well go totally unstable under such changeable conditions.....

Like was sais, if the TOPswitch design is from the PIXIS design suite, or from the PI Expert software, then your good.....but if not......then surely one is in danger of instability?

 

[cupoftea]

Thanks, and supposing TOPswitch is in Current Mode, then you would agree that nobody can produce Bode Plots for it, because the Sense resistor in the TOPswitch is not known, nor the current sense gain (if there is any!), and nor the gain factor of peak error voltage to peak current sense voltage.

So basically, if TOPswitch is Current Mode...we are stuffed, we cant assure stability unless we buy a gain phase analyser.

Unless we just do Load step tests and take advantage of the fact that for current mode converters, load step testing is generally all thats really needed. (ie bode plots not necessary)

The attached shows Dr Ray Ridley and The Vice president of product development of power integrations getting together to do feedback loop measurement on TOPswitch......but if its just current mode control....do we really need to buy a gain phase analyser.....i suppose if the crossover freq needs to be made very high or something...i had always thought that they did this PDF because TOPswitch was Voltage Mode and they therefore wanted to help people avoid Voltage Mode Dynamics issues.

1:55 to 2:30 of this shows Dr Mike Engelhardt generalising that Bode plots are possibly not generally necessary for current mode converters..

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...sounds to me like maybe the Vice President of Product dev in Power Integrations possibly missed a sales opportunity there? (if TOPswitch really is current mode).....i mean, shouldnt he have said, "hey guys, our TOPswitch is in current mode, and generally speaking you dont need Bode Plots or to go out and buy Gain Phase analysers for that"

 

[Easy peasy]

why confuse your average extremely junior EE who has been told to do the power supply - by mentioning something they cannot change - i.e. the internal control loops of the ToPswitch - just concentrate on closing the volt loop - which has been made extremely easy by having a big cap and small resistor on the comp pin - and a linear current level that sets the ref level for the curr signal inside the part - some PI parts go to 78% on time - so the slope comp is added automatically too - as is Vin feed-forward - which really reduces Vout ripple due to Vin ripple, keeping the total information limited to only that actually needed by the junior EE is a good marketing step.

 

[cupoftea]

Thanks, but ive worked for a lot of Engineering Managers who just won't have a voltage mode controller in any project, even if to be done by a Junior EE.
They wont look at TOPswitch because they read the literature and thought it was a voltage mode controller.
Its often you have to do a potential controller chip search for a certain SMPS project...and the gaffer says..."group together all the voltage mode ones and we'll bin them". I doubt a junior EE is going to be able to understand AN57 that well anyway. And if they are that free of knowledge that theyve never heard of current mode or voltage mode....then writing about it in the literature is probably irrelevant, -they probably wont read it anyway.
So you seem to think its in current mode, and the reason they say its in voltage mode, is because they want to make more sales?, because junior EE's would be put off if they mentioned current mode instead of voltage mode?

 

[Easy peasy]

note: " built in loop stability "

--- Updated Dec 30, 2024 ---

note the volt loop . . . unlikely this volt loop would work - if voltage mode alone.

--- Updated Dec 30, 2024 ---

all the way to this one :

--- Updated Dec 30, 2024 ---

p.s.

you only need leading edge blanking for pk current mode control - for straight volt mode the ramp and the volt error signal are not influenced by turn on current in the mosfet.

--- Updated Dec 30, 2024 ---

and:

 

[mtwieg]

I love this bit because the output voltage is indeed regulated by a voltage loop, and it is pwm based, CMC is neatly avoided so as not to confuse the newbies

I disagree that not using the term CMC avoids "confusing the newbies", especially since they haven't substituted it with anything coherent. CMC is not a novel concept, anybody working with SMPS should be familiar with it.

Note the talk of cycle by cycle current limit ( impliedly to perform pk curr mode ) - why have this and not use it down to 55% to get far better system dynamics in CCM ? - are you saying the PI guys literally decided to abandon a superior strategy and skip over to volt mode only - making their product super hard to stabilise above 55% current ? yeah right.

QED.

The thing that doesn't sit well with me is that if you're correct and the part continues to operate in CMC above the 55% threshold (I think this is what you're claiming), then why would they go out of their way to state the exact opposite in their literature? It doesn't make sense from the perspective of making things more digestible for "clowns" or whatever slur you come up with. If they really wanted to simplify their datasheets they would simply eliminate all discussion of these topics and just point you to reference designs or a calculator on their website (i.e. the cookbook approach).

So they've failed to avoid confusing anyone, and at the same time end up suggesting they use an inferior control scheme under heavy load conditions, which experienced engineers are going to see as a red flag. It's a remarkable own-goal.

 

[cupoftea]

you only need leading edge blanking for pk current mode control - for straight volt mode the ramp and the volt error signal are not influenced by turn on current in the mosfet.

Thanks yes, but someone with a poor layout/design etc may get such a high turn on spike that it breaches the ultimate current threshold which is still there in voltage mode. So for that, the LEB would be useful even if in voltage mode.
See your point about "built-in loop stability" though...but that might also mean voltage mode with some internal "helping" mechanism.
The way to find out would be to compensate it such that if it was voltage mode it would go unstable, but would be stable if in current mode. Then see if it goes unstable. Though of course if its "voltage mode with some internal helping dynamics" , then that would mess that plan up. "Internal helping dynamics" is possible with a Power Integrations chip......they've done it with Innoswitch, which needs no user feedback compensation at all.

 

[cupoftea]

The attached LTspice Voltage Mode CCM offline Flyback simulation (with Bode Plots) shows how, as is known, Offline Voltage Mode CCM Flyback is certainly do-able.
With decent Crossover frequency aswell. Though admittedly eg the opto parasitics arent well modelled here.
Its not beyond belief that Power Integrations could have added some internal compensation "helping mechanism" into the TOPswitch to assist engineers
with the voltage mode dynamics if they didnt quite get it right.

Possibly Power Integrations did "Voltage Mode with internal , adaptive helping dynamics"(?)

An advantage of having the Voltage Mode "shell" would be that no Slope compensation would be needed.

 

[Easy peasy]

" built in loop stability " says it all, very much the " voltage mode with some internal "helping" mechanism. " of Mr. flyback / cup of tea

below 55% the mode is changed quite radically to variable freq - const peak current - this is variable off time control ( const on time ) which is very robust when controlled by the external volt loop - above that power level - where the peak currents are higher - one can also see from the various graphs they supply that the current hits exactly the same peak every time - under pure volt mode this would not be the case as there would always be some modulation of the on time as the Vin goes up and down.

QED.

--- Updated Dec 30, 2024 ---

@ Mtweig - when PI parts first came out - many years ago - they no doubt had an eye on the world of patents and possible infringements - keeping a methodology secret and in silicon - helps a lot in this regard. I'm not completely minded to discuss control aspects with anyone who does not immediately know there is no RHPZ under DCM in a flyback ( or boost or similar ).

 

[cupoftea]

above that power level - where the peak currents are higher - one can also see from the various graphs they supply that the current hits exactly the same peak every time - under pure volt mode this would not be the case as there would always be some modulation of the on time as the Vin goes up and down.

Thanks, but i dont see any such graphs showing what you suggest?
---___---___----__----___--____----___

DER234 (12V 18W CCM Voltage mdoe flyback
(page 33 shows Bode plots, page 6 shows schem)
Pse find attached here the double-checked Bode plot calcs for the DER234 by power integrations. (when at 115VAC input, and its voltage mode CCM)
I am not sure why you suggested that this would oscillate?
The Voltage mode power stage has a calculated double pole at 731Hz. The compensation zero's are at 188Hz and 99.5Hz.
As such the power stage double poles are well cancelled.

The Bode plots in the attached excel show decent phase margin at crossover for the DER234 schem.

The Error Amp Tran Func was taken from Basso's book "designing...." (pg 458 equn 8.10)
The power stage tran func was taken from Basso's book "SMPS" (pg231), but the gain constant bit ("kP") was taken from AN57 equn 11.

So you are saying that DER234 at 115VAC , and if was under pure voltage mode control.....you are saying that the shown schem would be unstable?

(Also Maybe the way they did the loop gain measurement and crossover measurement was a bit wrong...as can often be the case at the lower frequencies.)
___---___---___

I'm not completely minded to discuss control aspects with anyone who does not immediately know there is no RHPZ under DCM in a flyback

...you are speaking of Mtwieg's post #28?...MtWieg definitely doesnt say there is an RHPZ problem with DCM.

--- Updated Dec 30, 2024 ---

---___---___---___--____---_
My guess at this point, from all said, is that
TOPswitch is most likely to be in Voltage Mode.
Partly because doing adaptive slope compensation would have been an unwanted complexity.
So I also believe that they have some secret Voltage mode "helper dynamics" inside the TOPswitch.
So the user does a bit of external frequency compensation, and then the TOPswitch
does the rest and makes it stable...adaptively....adding such an algorithm to TOPswitch
would have been easier than doing Current mode and then having to do adaptive Slope compensation.

I point to Innoswitch as my proof of this...Innoswitch literally does the whole feedback compensation
internally...and I reckon they may well have used TOPswitch to kind of trial this feedback algorithm out in part....but with TOPswitch
there is still some need for some external feedback compensation, because they maybe had'nt quite sussed out the
way to do complete feedback compensation internally when they were making TOPswitch.

Where does this leave you when trying to select a controller for a Offline Flyback?....well, you look at TOPswitch
and the fact that the only thing you can assume is from what they actually say...ie that its a voltage mode controller...
….so this would put many people off from using it...despite people's suspicions that it will actually end up being OK. (due to the
suspected internal , adaptive, voltage mode, feedback loop "helper" algorithm.)

.....Many would just say..."forget TOPswitch, just use Innoswitch instead"....but Innoswitch only comes
in SMD footprint, and look at page 12 of DER535 (below) for the heatsinking method.

Show me a company that wouldn't boot an engineer off the job in seconds after seeing such a
complex heatsink assembly approach? (specially if sales volumes werent that high)

DER535 innoswitch -CE (65W flyback) -Pg 12 shows heatsinking

https://www.power.com/sites/default/files/documents/der535.pdf

 

[Easy peasy]

Here is a comparison of DCM vs CCM for pure volt mode - using very simple volt mode feedback loop:

the ramp is on C3 and the top point of the ramp - where the cycle terminates is controlled on pin 5 - CV ( simplest pwm control )

here are the results:

not too bad - even for a 3 ohm load on 14V - and an offset due to to the very simple zener control - as in fact shown for the ToP100 / 200 in datasheets.
Vout in purple, CV in blue.

Now for the same control with CCM:

C6 = red, Vout = purple, CV = blue
and the power circuit to get CCM:

changed the Tx only.
It is actually fairly difficult to devise a control ckt to give high bandwidth response to the CCM power ckt in volt mode only - you can up C4, C5, and C6 to slow the control loop response - and you can tame it that way - but the BW is low.
Shifting to peak current mode gives a whole new world where the volt loop can be closed at higher BW's and good control can be established.

--- Updated Jan 1, 2025 ---

And just for completeness here is the CCM in a fast volt control loop ( with output feed forward ) and Vin feed forward:

results:

which might look good until you consider the perturbation is only +/- 10V on 250V Vin, i.e. +/- 4%
for a 10% too 100% load step ( and back again ) on Vout - the performance will be pretty poor.
but - under current mode ....

--- Updated Jan 1, 2025 ---

and for load step, ckt:

results:

likely best case under any volt loop conditions.

--- Updated Jan 1, 2025 ---

zoomed in Vout:

 

[cupoftea]

Thanks, yes, but as the attached ti.com calculator shows, you can get high BW with pure voltage mode....eg the LM5145.
Here a 100kHz Buck has 20khz crossover and nice phase margin.
OK theres no RHPZ for Buck but even CCM CurrMode flyback has RHPZ.

Once you have got the type 3 compensator in there, and put the compensation zeros to cancel out the voltage mode power stage poles, you are
ready to get yourself a decent crossover frequency with voltage mode control. With offline flybacks the RHPZ is out at high frequency anyway in most cases.

I am not denying the current mode dynamics mean its a whole lot easier to get a stable converter....but just that with voltage mode if you can plot out your bodes, and ensure you cancel your output double pole with two zero's, then your fine with voltage mode control.
Here we see Dr Mike Engelhardt echoing this.....
(from 01:55 to 02:30.....)

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So yes, i still think we are talking at crossed purposes....we likely both agree that as long as you use a type 3 compensator, and you plot out your Bodes, and place your two zero's to cancel the double pole, then you are fine with pure voltage mode control.
But yes...as we probably agree, do a Voltage Mode converter without a type 3 compensator and without knowing where your compensator zeros are...and standby for disaster!

 

[cupoftea]

the performance will be pretty poor.
but - under current mode ....

Thanks,
We can trade Voltage Mode vs Current Mode situations till the cows come home.
As you know, we need the Bode plots to see what's really going on...and to see where the compensation poles and zeros have been placed.
The attached (LTspice) shows a Current mode and voltage mode flyback.
They have similar feedback loop compensators, and in this case, the voltage
mode one shows better performance, than the current mode one, including better response to Vin variation
as the low value HVDC cap is small and gives a lot of Vin ripple.

Also, IMHO, TOPswitch is voltage mode with internal "helper" dynamics. This makes more sense than
doing current mode, where, for a monolithic control/FET IC, doing adaptive slope compensation for
whichever spec the particular customer is designing to, would be over-complicated. As such, they did
TOPswitch in Voltage Mode.
The fact that TOPswitch is virtually the only remaining Monolithic Offline Flyback control/FET switcher IC on the market is testimony to their
wise decision making in this respect.

They could have just provided transfer functions so that users could self-compensate...but they
probably new that this might be problematic, so i believe they just put in the "helper"
dynamics without telling anyone.

The fact that their forum has virtually zero posts concerning users with feedback loop problems, it seems
very likely thay added the "helper" dynamics.

Its almost impossible to see how SMPS beginners for example, would all manage Type 3 Voltage Mode compensation without getting into problems.
As Mike Engelhardt says, with Voltage Mode you need to calculate out the Bodes, and its impossible to see how SMPS beginners wouldnt struggle and
stumble on this.
In fact, if a company is prepared to give over the full spec and details of the design, Power Integrations
will actually take an offline flyback design in as an "owned design", and will design it all for the company,
which obviously means the company has no problems with loop stability.

Innoswitch of course, is only "helper" dynamics, and there
is no need for the user to do any loop compensation at all. I'd say its a guess but this internal dynamics was likely
part trialled in the TOPswitch.
This is only my opinion, but i believe it seems the most likely situation.

__---__---_-----__
The following App Note by Mammano tells the differences between voltage mode and current mode.
As is seen, voltage mode has advantages when thinking of multiple output rails.....offline flyback specs often have eg a 24v a 12v and a 5v output spec, so voltage mode then looks favourable...

https://www.ti.com/lit/an/slua119/slua119.pdf?ts=1735785154414&ref_url=https%253A%252F%252Fwww.google.co.uk%252F

Combine voltage mode with a type 3 compensator and you're laughing....Put two compensator zeros at the power stage double pole, one compensator pole at the esr zero, and the other compensator pole at the RHPZ frequency, and you've likely got a good PSU with a respectable feedback loop BW

___---___---___-
And the advent of synch buck controllers is bringing Voltage Mode right back to the fore....because in current mode, you need a high side current sense amplifier and high side error amplifier to read it with.....often making the IC expensive...whereas voltage mode can do it with a low side resistor and simply use it as an overcurrent detector.
Then again "emulated current mode" has also come into it.
But its noticeable how some of the cheapest synch buck chips are voltage mode. They usually offer excel docs showing feedback loop bodes all done for you....and really super high crossover frequencys without any problem. (eg LV5144 is the cheapest Synch Buck controller for 48V+ inputs and its voltage mode)

 

[Easy peasy]

Respectfully - you can't get any where near the dynamics of the PI parts without an inner peak ( or in one case average & peak ) current mode loop - closed externally by the volt mode loop - which one must have to stabilise Vout.

Volt mode only would be a nightmare for the user - and always leave a nasty niggle of an oscillation at higher powers in CCM.

 

[cupoftea]

Thanks but what sort of crossover's have you been getting may i please ask?, bearing in mind that all TOPswitchs feature a fixed internal 7kHz pole.
Also, why dont they say its current mode?, and why do they have feedforward if its in current mode?
And you are saying HiperTFS is current mode aswell?......even though PI also say its voltage mode.
And wouldnt Basso have noticed this?...before he dedicated the entirity of his chapter 8 "Designing control loops..." to TOPswitch, where he makes multiple references to it being in voltage mode.
The attached is from Basso's book pg 456....showing a Voltage Mode Controller inside TOPswitch....pse also not the 7kHz pole.

__---__--
Also, as page 314 of Basso's other book "Switch mode power supplies" tells, the TOPswitch
designer is advised to use a 47uF Cvcc capacitor at the TOPswitch Vcc pin. With the
resistors nearby, this means another pretty well fixed pole at
around 155Hz for the TOPswitch. So with poles of 155Hz and 7kHz
imposed on your TOPswitch design, getting a really high crossover frequency isn't going to be possible
anyway. Admittedly the Cvcc.(Rd+Rs) pole does get cancelled by the Cvcc.Rs zero, but it shows that that zero cant be used
in boosting phase at some higher frequency for a high crossover.

 

[Easy peasy]

Basso has inferred quite wrongly here - showing that people are not infallible - however he is not entirely to blame as the prose offered by the company at the time was intended to be obfuscatory, for reasons given above.