harshpar1
Newbie level 4
Clock nets and asynchronous resets are generally specified as being ideal during synthesis. It is the responsibilty of the layour engineers to lay the clock tree and the reset tree so that the skew is within limits and that the circuit meets timing.
However my question is:
How are synchronous reset nets dealt with during synthesis? These nets are high fanout nets as well (similar to clock and asynchronous reset nets). How do I specify a synchronous net as being ideal. The synopsys design compiler does not let me specify an internal pin as being ideal. Can anyone let me know what is the correct procedur of specifying an internal pin as source of an ideal network?
However my question is:
How are synchronous reset nets dealt with during synthesis? These nets are high fanout nets as well (similar to clock and asynchronous reset nets). How do I specify a synchronous net as being ideal. The synopsys design compiler does not let me specify an internal pin as being ideal. Can anyone let me know what is the correct procedur of specifying an internal pin as source of an ideal network?
