pulse width stretching

[barry]

Two single ST gates and an AND.

Just use a single ST AND, e.g., 74HC7001, or two NANDs. No reason to use two packages.

 

[andre_luis]

What'S an ST gate?

Whenever you read ST (Schmitt trigger), it refers exclusively to the input stage; which is a voltage range at inputs logic that do not submit any change to the output stage, a kind of noise filter to avoid unexpected effects from slow slew rate inputs, such as the RC circuit posted above. Anyway, this answer is easily found on the Web.

 

[FvM]

Just use a single ST AND, e.g., 74HC7001, or two NANDs. No reason to use two packages.

I'm talking about circuit functions not IC packages. They asked about "designing" the Schmitt trigger although no technology has been mentioned yet.

 

[iaf]

so how would i design this schmitt trigger with 2 inputs?

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another problem with this design is that the pulse will be stretched in a constant time regardless how long the input takes, which is applicable in case if the input is longer the RC time constant, so is there a solution to add this time constant to the original width?

would this design solve this problem?

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and is there any source where i can find more detailed information on this topic?

 

[iaf]

here's and image of the output

 

[FvM]

The RC delay solution has the problem that the extension time reduced for short negative pulses because the capacitor isn't fully discharged. This can be handled by a diode across the resistor.

You can sketch the capacitor waveform to visualize the delay operation.

 

[barry]

View attachment 153709
here's and image of the output

Is this what you want, or not? If it is, my original suggestion does exactly this. I think it’s time now for you to provide more specifics of exactly what you want. Min/max input pulse width, output pulse width etc. it’s becoming less clear whether you want a pulse stretcher, edge-triggered one-shot, or what.

 

[iaf]

The RC delay solution has the problem that the extension time reduced for short pulses because the capacitor isn't fully charged. This can be handled by a diode across the resistor.

That's not a big problem, the main problem is when the pulse is longer than the T

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Is this what you want, or not? If it is, my original suggestion does exactly this. I think it’s time now for you to provide more specifics of exactly what you want. Min/max input pulse width, output pulse width etc. it’s becoming less clear whether you want a pulse stretcher, edge-triggered one-shot, or what.

yes that's exactly what i want. It was introduced to me as a pulse stretcher i don't know if it's the right terminology. Min pulse width could vary let's say from 500ns to a couple of ms. The output pulse width that i would have is ca. 50-100ms

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Bad idea. Use this:

View attachment 153653

Have to consider pulse width, etc. in selecting RC. Can also put diode across R for narrow input pulse.

so i can achieve that by using an AND gate and RC?

 

[FvM]

There's no problem with longer pulses, you seem not to understand the circuit operation. Suggest to perform a simulation. Please report if you see problems with it.

 

[iaf]

There's no problem with longer pulses, you seem not to understand the circuit operation. Suggest to perform a simulation. Please report if you see problems with it.

here's the circuit and here's the result of the simulation when setting the input pulse longer than the time constant

 

[barry]

What’s the duty cycle? If you have 500 ns pulses with a 50% duty cycle, there won’t be time for the cap to charge (as has been pointed out). And what’s the stretch-time? In order to do a proper design, you need ALL the information.

 

[iaf]

What’s the duty cycle? If you have 500 ns pulses with a 50% duty cycle, there won’t be time for the cap to charge (as has been pointed out). And what’s the stretch-time? In order to do a proper design, you need ALL the information.

the duty cycle is varying it could be anything as this is a trigger for a reset signal. and the stretch time is ca 50-100ms as mentioned

 

[barry]

So you're going to need to put a diode across the R so that the cap charges fast.

 

[iaf]

So you're going to need to put a diode across the R so that the cap charges fast.

ok i still didn't get the design you meant. Is it an AND Gate with the RC connected to one input?

 

[barry]

You need to do some actual engineering here. Here's what you need to think about:

If you use the circuit I showed in post #12 you need to ensure that the input pulse is wide enough (low) to completely discharge the cap. You also need to ensure that the pulse high-time is long enough for the cap to completely charge. These are the limitations of this circuit. You can play some games with diodes; for instance, if your low time is short but your high time is long enough, you can put a diode across R to discharge the cap faster. If your requirements don't meet these limitations, you'll need to think of a different (i.e., more complex) approach.

 

[iaf]

You need to do some actual engineering here. Here's what you need to think about:

If you use the circuit I showed in post #12 you need to ensure that the input pulse is wide enough (low) to completely discharge the cap. You also need to ensure that the pulse high-time is long enough for the cap to completely charge. These are the limitations of this circuit. You can play some games with diodes; for instance, if your low time is short but your high time is long enough, you can put a diode across R to discharge the cap faster. If your requirements don't meet these limitations, you'll need to think of a different (i.e., more complex) approach.

i got your point and i want to simulate your approach that's why i'm asking how to realize the circuit you drawn itself

 

[barry]

I'm not sure what you're asking.

 

[iaf]

I'm not sure what you're asking.

Realizing this schmitt trigger with 2 inputs

 

[barry]

I still dont know what you mean by "realizing". What is your simulator?

 

[iaf]

I still dont know what you mean by "realizing". What is your simulator?

I'm using Cadence so i have to implement it whether as digital gates or transistor level