problem with LDO design!

[ashish_chauhan]

to measure the quescient current you can do this:

separate the ground connection of load and ldo... then connect the ground of ldo to main ground through a voltage source of zero value. The value of current through this voltage source is ur quescient current.

refer to digram attached it will be clear.

or the simplest way... just operate ur ldo for zero load current ... what ever is the current drawn from vdd is ur quescient current...

hope this helps.

 

[LvW]

well its right that pm is defined at freq where gain is 0dB. but u need to ensure enough margin through the loop bandwidth because as the corner changes some of the parasitic poles may get in the bandwidth range and degrade ur good margin.
we never encourage this kind of phase response... it is always risky!!
imar, I wont recommend this specially when its a typical response.

Hello ashish_chauhan and imar

I´m sorry, but again I have to comment on ashish_chauhan´s reply.
Imar, don´t worry about the phase margin - it´s really OK.
I think, some theoretical aspects come into the play now.
It may be surprising for both of you, but even in case that the phase response reaches or crosses the zero deg. line (before it again goes high due to the compensation network) the closed loop will be stable !! Therefore, it is not "risky" as ashish_chauhan has claimed.
This is according to the very well known NYQUIST stabilty criterion - and it is the base of the method of lead compensation which is very often applied in control systems.
Of course, it would be better to have even more phase margin, but realize:
Every analog design is a compromize between conflicting requirements.
You cannot improve any margin without a negative influence on another parameter.
For example, reducing the output capacitor will increase the margin, but the smoothing capabilty of this cap will go down. So, a good analog design is more or less an "art" and is equivalent to a kind of balancing parameters to find the best compromize. Hopefully, I have expressed myself clear and you can understand what I have tried to say.
Regards to both of you.
.

 

[ashish_chauhan]

For LvW:

It is really amazing to know that even if the phase crosses zero point and stays there for some time(frequency range) with gain being positive the system will not oscillate...!!

what about the barkhausen criterion... can u suggest one example where such a case can happen...

as soon as u turn on the circuit it may catch up with one of the freqs in the dip(where zero crossing happens) and will never come out of it...

 

[imar]

hello Ashich_chauhan and LvW
what should i say ?

it is really a great time that i am spending with you two!

For LvW, these theoretical aspects are so nice to inderstand especially concerning the NYQUIST plan.

for Ashich_chauhan, i tried the last solution to simulate the quiescent current, and... well done the quescent current is around 16.45µA.

thanks again.
i will go to dig in the Layout aspects and requirements that shoulb taken in account to achieve the Layout of the circuit. if there are some guidelines, it would be so nice especially for the big pass element!!

thanks again

 

[LvW]

For LvW:
what about the barkhausen criterion... can u suggest one example where such a case can happen...
as soon as u turn on the circuit it may catch up with one of the freqs in the dip(where zero crossing happens) and will never come out of it...

Well, this is not the right place to explain the background of NYQUIST´s criterion, perhaps you have the chance to read something about it in books.
The content of the criterion is in short: The NYQUIST curve of the loop gain must NOT encircle the critical point within the s-plane if the closed system is stable. That means, the critical point (+1 or -1, depending on your diagram properties) is required to remain outside of the NYQUIST curve.
As far as BARKHAUSEN is concerned: There is a severe misunderstanding regarding the background of his criterion, which even can be found in several books. I even have found the phrase "Barkhausen is wrong; down with Barkhazsen".
The mentioned misunderstanding is as follows: The well known Barkhausen criterion is NOT a sufficient one, but "only" a necessary condition to be fulfilled for a circuit to oscillate. That means, if a circuit oscillates, the loop gain is equal or greater than one. But, on the other hand, if the loop gain is one (or>1) for a certain frequency, this does NOT mean that the circuit must oscillate or is unstable.
It´s interesting and also important to know.

 

[ashish_chauhan]

Well then shall I take it this way:-

Even if the phase shift is more than 180(apart from 180 of negative feedback),
and the gain is >= 1 the circuit "may or may not oscillate..."

if so then what is neccesary and required condition for oscillations?

can u provide some literature which can clear my confusion(if it really is) in this regard. please dont point to some thing which talks in terms of mathematics.

thanx!!

 

[LvW]

..........
................................................
if so then what is neccesary and required condition for oscillations?

Congratulations ! This question is the logical consequence of our discussion !
And - be sure - I have the same question in my mind.

But I have to disappoint you: Up to now I didn´t find an answer to this question.
To make it clear: I don´t know any book or paper in which a SUFFICIENT oscillation condition is formulated. Of course, the BARKHAUSEN condition (loop gain=1) has to be fulfilled (which is necessary) - but something more is required to be sure that a circuit can oscillate. But I don´t know what is this "something more".
I face this problem since several years ! Do you - or anybody else - have any answer ?
Regards

 

[ashish_chauhan]

Sorry... but I will again say something similar to my previous posts .

The case to which LvW is referring ... is probably called conditional stability.

Due to which theoretically we can declare a loop to be stable even if its phase crosses the zero line and comes back before the 'Fc'(where gain becomes one or '0'dB) .

This as I said is risky becoz if during the startup of circuit the loop gain reduces and become 0 db in the phase dip range(which it really can) may cause the circuit to oscillate and may never settle down.

LvW I have attached a discussion on control loops please have a look and comment.

 

[LvW]

The case to which LvW is referring ... is probably called conditional stability.
Due to which theoretically we can declare a loop to be stable even if its phase crosses the zero line and comes back before the 'Fc'(where gain becomes one or '0'dB) .
This as I said is risky becoz if during the startup of circuit the loop gain reduces and become 0 db in the phase dip range(which it really can) may cause the circuit to oscillate and may never settle down.

Yes, you are totally right: When at a certain frequency the loop gain phase is zero with a gain>0 dB, and when the phase for higher frequencies goes again up due to a lead correction network, this is called "conditional stable" !
Of course, this situation can be called "risky" - however, in many cases there is no way-out of these conditiones and one has to live with.
And don´t forget in the case under discussion the minimum phase is something around 30 deg (and not zero) - therefore it can be considered as sufficient safe.

As far as the last sentence of your reply is concerned, even in this case as described by you there will be no oscillations because the Nyquist criterion applies - and this holds for the steady state condition. But again, I agree that such a design should be avoided if possible !
I think, nevertheless, it´s an interesting and challenging subject. Thank you.
Regards

 

[ashish_chauhan]

yes u r right ... it is interesting and intriguing as well.

Thanx for ur final comments


bye the way can u provide me some good paper or material on gm/id approach...

I am trying to work out things that way...

regards
Ashish

 

[LvW]

bye the way can u provide me some good paper or material on gm/id approach...
regards
Ashish

Unfortunately, I have no experience at all with the gm/Id approach.
However, I found in my library one paper dealing with this. Perhaps it helps.
Regards

 

[ashish_chauhan]

Thanx , but this is some thing i already had.

regards
Ashish

 

[imar]

hi again freinds;

we have spoken later about the positive and the negative feedback for the error amplifier and hopefully as LvW said, the PM is not always calculated by taking the origin in -180° and LVW has well explained it. so at this point, a question could be put: what is the difference between having a positive feedback or a negative one? how could we choose between them?
in what point does this feedback affect ?

thanks for information in advance!

regards

 

[LvW]

Hi imar !

For two reasons I suggest you to open a new topic with this question:
1.) We are already on page 3 of the LDO page
2.) It is, indeed, an interesting question which deserves some comments.

Do you agree ?

 

[imar]

hi LVW!
ok, as you suggeted!

i really forgot that we are already in page 3.

i will post the question again and the title will be: positive and negative feedback in LDO design.

it seems to be a very helpful conversation concerning this issue.

 

[LvW]

I suggest NOT to restrict the discussion on LDO design.

 

[imar]

ok ,
i eliminated the 'in LDO Design'.

 

[imar]

hi again!

after measuring the PSRR of the LDO approximatly with tran response as we discussed in page 2, i achieved the PSRR simulation with AC simulation by making a AC component 1 to the Vdd and by fixing the output current to 10 mA.

the result of the simulation is reported here, so could any one commentate it please ?



thanks for response

 

[ashish_chauhan]

well it looks extraordinarily good!!!

are you sure there is no mistake in the ur setup ...
have you included the extrinsic capacitors in the simulations...

... If yes then its superb...!!! just rerun the simulations for Iload =100mA.

also check are u getting the dip in psrr curve at a same frequency as is ur loop bandwidth.

 

[imar]

HELLO ASHICH-CHAUHAN!
thanks for response!

i run the simulation with the requement that you have fixed in one of your replays: AC component in the Vdd and running the AC simulation.
you will find joined the PSRR for load current of 100mA.



concerning the comparaison between the location of the deep in the PSRR sim and the loopbandwidh gain : hopefully, it is quite the same for a frequency that goes in 2KHz





thanks !