problem with LDO design!

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replace pmos nmos

hi freinds!
i found some problems duriny=t the design of a Low Dropout Regulator:
this regulator should have: Vdropout:0.5V, so with Vin 3.3V , Vout must be 2.8V.
the load resisttance goes from 28Ω to 2.8KΩ. the Load capacitor is 2.2µF
this regulator has : * a PMOS pass element W=6µ/L=1µ.
* Error amplifier with 60 dB
* bandgap 1.2V
* a frequency compensation scheme
i designed each element apart, and i verified the functionnality of it.
But, when i reessemble the circuit, the circuit goes nice with load resistance of only 2.3KΩ to 2.8KΩ ( current about 1 to 20 mA approximatly).Ifound that Vout is 2.8V and the stability is about 50° as phase margen.
However, if the Rload falls to 1KΩ or less the regulator ceases to work; infact Vout become 3.8V (which means, i think, (Vin)3.3V + (Vdropout)0.5 V) and the circuit is not stable.
is it about the pass element or some thing else?

thanks in advance for any response that may help me!
 

imar said:
........................... * a PMOS pass element W=6µ/L=1µ.
* Error amplifier with 60 dB
* bandgap 1.2V
* a frequency compensation scheme
Click to expand...

What kind of frequency compensation circuitry do you use ?
 

So, the W/L ration of your pass element is 6???
It seems to me very small, there could be 100 mA with the smallest load...
 

thanks!
it is a capacitive feedback frequency compensation which acts as voltage controlled current source. it introduces a left hand plane zero inthe feedback loop to replace (in case we used the ESR compensation method) the zero generated by ESR of the output capacitor.this method allow theoretically to control the zero location and minimize the overshoot.
you will find joined the regulator circuitry and the compensation scheme too.
thanks
 

sorry Drabos!
W is not 6µm but 6mm and L is 1µm.
it is a taping mistake sorry.
thanks
 


As far as I can see, your circuitry looks like a classical LDO configuration - and from your diagram I cannnot derive any arguments explaining the problems mentioned.
Question: Did you simulate the circuitry with an appropriate program already with different values for the compensation cap C1 ?

Added after several minutes: What is the purpose of the cap at the OTA output (parasitic or extra element) ?
 

you 've right, it is a classical LDO since it is my first steps with LDOs, and i want to initiate with this type of regulators.
first, i am handling Cadence envirenment to simulate the circuit and to verify the design and i simulate the circuit for some value of the capacitor C1 which is added (not parasitic)to achieve the capacitive feedback and thus to introduce the required zero. its value is 5pF and by the use of the frequecy compensation circuitery, the effective capacitance will be 25 pF to push the parasitic pole beyond 1Mhz which is the Unity Gain Frequency.
another thing, when i simulated the hole circuit the AC gain is only around 8 dB with a phase margen about 50°. so i think that the frequency compensation scheme must have a little gain since it comes in the feedback loop, isn't it?
moreover, is the size of the pass element (6m/1µ) enough to reach a load current of 100mA?
is it trut that, when i changed the load resistance value from 2.6KΩ to 100Ω, the pass element should be bloqued to maintain Vout at 2.8V? because, i found that Vout become 3.8V as if it has ineversed her function: 3.3-0.5=2.8V and 3.3+0.5=3.8V?

thanks
 

1.Q: Are your results derived from measurements or just from simulations ?
2.Q: What is the purpose of the cap at the OTA otput ? (It can degrade stability !)
 

hi!
for the first question: these results derived only from AC and transcient simulations.
for the second question: if you are speeking about Caux, it is only a parasitic capacitance , the same thing for the Cparasit
but if you speak about C1, it is the capacitance that allow the frequency compensation having that the location of the zero is given by wz= 1/R2C1. i tried to change this capacitance and i found that it could regrade the stability in some cases.
 

OK, I spoke about Cpar at the OTA output because it influences stability. But if it is parasitic you cannot do anything against it.
The role of C1 is clear - it produces a zero which is necessary for stabilty reasons.
However, I really don´t know how your circuit can produce 3.8 volts with a Vdd=3.3 volts. I suppose that your circuit is unstable ! Are sure about the phase margin of 50 deg ? How did you arrive at this value ?

But I have another question: What is the reason to show a diagram in which the passive compensation scheme with C1 is replaced by an active circuitry with two controlled current sources ? I suppose, the hardware realization will be the passive one ? But for which purpose the active alternative ?
 

hi and thanks lvW!
the phase margen is 50° only for a loard resistance that goes from 2.3KΩ to 2.8KΩ and in this case the Vout is 2.8V.
but if i decrease the load resistance, the circuit become unstable and Vout is 3.8V.
on the other hand, this topology of compensation scheme is based on the fact that if we use only C1, this will create not only a zero but a parasitic pole which should be elemineted, so came the idea to eliminate the pole ,which is
wp=(1+R2/R1)/R2C1, without affecting the zero.
you will find attached the paper that i am dealing with.
the results of simulation that i found, after re-sizing the most of transistors are the same. but when i simulate the frequency compensation, the results of the gain simulation compared to figure 7 have the same shape but the gain goes from
-20dB not from -150dB which make some doubts about stability of my circuit and esspecially, i found that the gain of the entire LDO is around only 8dB.


the attachment:

thanks again.
 


Sorry, but I can`t read the attachement, because: The topic or post you requested does not exist (it was removed)

Question: How do you compensate/eliminate the mentioned parasitic pole ?

The fact that low load resistances causes instability is an indication that something is not properly designed within your compensation circuitry. Did you simulate the loop gain for different load conditions ?
 

sorry for the disturbance again!
you will find joined this time a summury of this paper,
concerning the elimination of the pole, this frequency compensation sheme allow the rejection of it by simply increasing the effective capacitance C1 which become as if it is egal to 25pF after enhancing the transconductance gm by the use of the OTA.
The fact that low load resistances cause instability is the fact that trouble the design because when i simulate each element apart, i didn't find any problem.
i simulated the gain loop by an AC simulation and the gain is always around 8 dB, which means that regulator is not already regulating and is not playing his true role and i don't knew why although i tried to vary different values of capacitor and also the size of the pass element, it didn't go only for few load resistance value?

thanks !
 

OK, now I´ve got the document.
One comment to the loop gain simulation profile, as a gain of only 8 dB is in fact a bit low (although I don´t know the OTA parameters):
Of course the circuit must be biased correctly - also for an ac analysis. This means that VDD has to be applied as a fixed dc voltage.
More than that, the ac source has to be placed such that the dc operating point is not damaged. How did you manage this ? It happens very often that the loop gain simulation is wrong because of no proper placement of the ac source.
A correct loop gain response is the basis for a good working compensation scheme.
 

thanks again!
to fixe the operating points of all transistors that form the LDO i achieved a dc simulation.then, i applied the ac source to the VDD because there ara only two inputs which are VDD and the bandgap input. so, should i take an ideal ac source and place it at the Voltage reference input to perform the simulation of the gaon loop?
thanks !!
 

Exactly this was my assumption: False loop gain simulation !

The term "loop gain" implies that the gain around the loop is calculated. However, neither the voltage VDD nor the reference voltage are part of the loop. Therefore, to insert an ac source within the loop you have to BREAK the loop at a suitable point.
My proposal: Insert an ac source BETWEEN the positive OTA input (point A) and the middle between R1 and R2 (point B). Apply all dc voltages (VDD and reference).
Then perform an ac analysis and plot db(V(B)/V(A)). This is the loop gain which must exhibit sufficient stability margin. Try it and report the result.
 

thanks LvW!!
i will try your proposal and i will report the results soon!
 

Hi !
sorry for the late LvW!
i tried to achieve the simulation of the gain loop as you said and i found that the gain becomes approximatly 35 dB.
so you will find the result of the simulation within Cadence!
i think that there is a problem concerning stability.
in this time, the output voltage don't reach 3.8V but only 3.2V
another thing, have i to pay more attention on the pass element?

thanks

Added after 7 minutes:

i forgot the print screen
 

imar said:
......... i found that the gain becomes approximatly 35 dB.
..........i think that there is a problem concerning stability.
in this time, the output voltage don't reach 3.8V but only 3.2V
Click to expand...

I think, in principle, the loop gain response looks good.
But you are right, the phase margin with app. 33 deg could be somewhat larger.
This can be achieved easily by adjusting the compensation parts.
At the same time, perhaps, you have to increase the gain of the error amplifier as in your first post you have mentioned gain=50 dB.
However, I don´t understand the mentioned voltage values.
At which point within your circuit and from which simulation (ac or tran) do they originate ?
 

if you created the dominant pole using the compensation, the stability should be better when theload resistance decrease, isn't it? If you designed the dominant pole to be at the output stage, then it may be a problem once the the load resistance decrease.
 

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