[SOLVED] Positive or Negative going Pulses or Edges

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danny davis

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How do you know when a signal or pulse is Positive or Negative going edge?

How do you know when A CIRCUIT is triggered is on the rising edge or falling edge?

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How do you know when a signal, pulse, clock, etc. is triggered on the leading edge or falling edge?
 

A pulse by definition has two edges, one at the start and one at the finish. Perhaps you are misunderstanding the terms 'positive' and 'negative' in this context, by positive edge we mean the edge where the voltage goes more positive than it's negative state and negative edge means the edge where is goes more negative than it's positive state. In other words the change from - to + is the positive edge and the change from + to - is the negative edge. It doesn't necessarily mean the voltages are positive or negative relative to ground, it's the direction of change that matters.

Without detailed schematics it isn't possible to tell which edge a circuit triggers on. In almost all cases the edge is detected by logic inside an IC so you would have to rely on the manufacturers data sheet to sheet to find out.

Brian.
 

Without detailed schematics it isn't possible to tell which edge a circuit triggers on. In almost all cases the edge is detected by logic inside an IC so you would have to rely on the manufacturers data sheet to sheet to find out.
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When looking at a schematic what are something things to look out for or signs that will tell you that the circuit is TRiggers on a positive edge or negative edge or leading edge or falling edge

How do you know if the clock pulses are a positive edge or negative edge or leading edge or falling edge? when I put my probe on the clock output or the clock buss , how can you tell?

In almost all cases the edge is detected by logic inside an IC so you would have to rely on the manufacturers data sheet to sheet to find out.
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What is inside the IC chip that determines that it detects on the Positive edge or Negative Edge? or Leading edge or falling edge?

Is it a Logic Gate?
 

I already answered the first part of your question. It depends on the schematic. Lets take an example: A heat sensor has an output that goes from 0V to 5V when it sees 100C, it is supposed to set off an alarm to say something is overheating. Would you expect it to sense the change from 0V to 5V to trigger the alarm or would you expect it to sense the change from 5V to 0V ???

Yes, of course it's a logic gate, that's what logic ICs are made of. As to the electrical difference inside the logic gate, the input has to overcome an internal 'pull' towards one logic state or the other. For example, it would be pointless to detect a negative edge on an input that was already low. The decision as to which edge is up to the IC manufacturer and most make devices for both scenarios so they can be used in different situations.

Brian.
 

danny davis said:
How do you know if the clock pulses are a positive edge or negative edge or leading edge or falling edge? when I put my probe on the clock output or the clock buss , how can you tell?
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You simply look at the datasheet of the counter IC that is being clocked!
 

You simply look at the datasheet of the counter IC that is being clocked!
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There is no counter IC chips, so how else do i find out how a clock is positive edge going or negative edge going?


CLOCK SOURCES
1.) Crystal
2.) Oscillator
3.) Timer ( which is an oscillator right? what's the difference between a timer VS an oscillator?
4.) What other types of clock sources?

A circuit board I'm troubleshooting uses a Crystal that goes to SN5404 Logic Inverter that goes to SN5475 Positive going edge Flip Flop

Why did they use a Positive going edge flip flop? than a Negative going edge flip flop? what is the difference?

Putting a Inverter buffer on the output of a Clock or Crystal converts it from a negative going edge to a positive going edge?

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They also put the non-inverter buffer schmitt triggers to CLEAN UP or sharpen the edges to square off the Crystal or clocks

The tech next to me said that there is a DELAY or phase shift on the LEADING EDGE when GATING or CLEANING up an analog signal or from a crystal, is this true?

He also said that when clock signals are HIGH frequencys that the leading edge of the clocks edges are rounded off, why is that? why are they rounded off?

There is some logic circuits that use UNregulated 5 volts , what Logic IC chips can you use unregulated 5 volts? because it will have some ripple on the 5 volts , i thought Logic circuit didn't like this

They use the unregulated 5 volts for RAM IC chips and other Logic IC chips

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Also the tech said that you can not use the ext. trigger on O-scope for TTL clock signals or TTL timer signals because you don't know where the Trigger to start from, there is no beginning or starting point.

So you can't use the ext. trigger on the O-scope for TTL clock signals? Because how do you know which "CLOCK PULSE" is doing the triggering or resetting? or enabling on the logic IC chips? how do you find out which clock pulse number is doing this?
 

danny davis said:
There is no counter IC chips, so how else do i find out how a clock is positive edge going or negative edge going?
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As someone already said, you look at the datasheet for the chip in question. It will always say if a trigger input is positive going or negative going.
Putting a Inverter buffer on the output of a Clock or Crystal converts it from a negative going edge to a positive going edge?
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Well, it will turn positive-going edges into negative-going edges, and vice versa.
The tech next to me said that there is a DELAY or phase shift on the LEADING EDGE when GATING or CLEANING up an analog signal or from a crystal, is this true?
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All chips that process signals add some delay - some more than others.
He also said that when clock signals are HIGH frequencys that the leading edge of the clocks edges are rounded off, why is that? why are they rounded off?
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Not true. There is no reason why high frequency edges should be any more rounded off than low frequency edges. High frequency edges just look more rounded off on the scope because when you are looking at a high frequency signal, you probably have the scope set to a faster sweep rate, which makes edges look more rounded.
There is some logic circuits that use UNregulated 5 volts , what Logic IC chips can you use unregulated 5 volts? because it will have some ripple on the 5 volts , i thought Logic circuit didn't like this
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As long as the ripple is not too high, and the power stays within the specified operational range for the chip in question, even an unregulated power supply can work. You can find out what the specified operation power range is in the datasheet for the logic chip in question.
Also the tech said that you can not use the ext. trigger on O-scope for TTL clock signals or TTL timer signals because you don't know where the Trigger to start from, there is no beginning or starting point.
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That makes no sense. You will have to ask that tech again what he meant.
 

High frequency edges just look more rounded off on the scope because when you are looking at a high frequency signal, you probably have the scope set to a faster sweep rate, which makes edges look more rounded.
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So it this an O-Scope resolution problem? I need a better O-scope with more resolution?


He said , with a TTL clock or CMOS clock, you don't know where or which clock pulse is the one that is used for triggering or for pulsing an IC chip? because a TTL or CMOS clock is free running

What he means is, which clock pulse is the one that is ENABLING the IC logic Clock pin or Reset pin?

As someone already said, you look at the datasheet for the chip in question. It will always say if a trigger input is positive going or negative going.
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So it isn't the Clock or timers output that determines if it's positive going or negative going?

Because some Clocks outputs are positive going and other clocks outputs are negative going , you don't need to use inverter buffers smitt triggers on the output of a clock to convert it from positive going to negative going , it's built into the clock



How do you know when a SYNC signal is positive going or negative going?

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TTL clock signals are free running, so you don't know which clock pulse is the Triggered event, so how do you find which clock pulse is the triggered event? because a TTL clock output is a free running pulse train
 

Danny,
Your silly questions show that you do not know and do not understand simple electronics logic circuits.
 

well the techs next to me are giving me this information , that's why I ask you
 

danny davis said:
So it this an O-Scope resolution problem? I need a better O-scope with more resolution?
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No, the rounded look of an edge when a higher sweep rate is selected would appear on any O-scope, because the edge really is slightly rounded. But then so are all edges, even low frequency edges, if you look at them at that same high sweep rate.
Of course you can know which edge is active. You just look it up in the datasheet of the chip it is going into.
All clock outputs have both positive and negative going edges, and when they are connected to inputs of some chip, that chip will use whichever edge it is designed to use. But some circuits, to work properly, must use a certain edge, so you can't always pick an edge at random. That is why it is sometimes necessary to invert the clock before it goes into an input. And many times it does not matter, so no inverter is needed. It all depends on the larger function of the circuit.
How do you know when a SYNC signal is positive going or negative going?
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The question makes no sense. Every sync signal goes high, then low, then high, then low, etc. It always has edges of both types.
TTL clock signals are free running, so you don't know which clock pulse is the Triggered event, so how do you find which clock pulse is the triggered event? because a TTL clock output is a free running pulse train
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As I and other have said many times, you look it up in the datasheet of the chip it is going into.
 

No, the rounded look of an edge when a higher sweep rate is selected would appear on any O-scope, because the edge really is slightly rounded. But then so are all edges, even low frequency edges, if you look at them at that same high sweep rate.
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Why are the edges rounded? what is causing the edges to be rounded?

Of course you can know which edge is active. You just look it up in the datasheet of the chip it is going into.
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What component inside the IC chip it is going to that determines which edge is active? what kind of component determines this?


So it's not the CLOCK signal that determines the which edge is active , it is the IC chip that is going into that determines which edge is active

. That is why it is sometimes necessary to invert the clock before it goes into an input. And many times it does not matter, so no inverter is needed.
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I have seen when it inverts the clock signal and other times is doesn't use an inverter to invert the clock signal

So why does it need to invert the clock signal sometimes? and other times it doesn't need to invert the clock signal?

The Inverter IC chip must NOT convert the clock signal to a negative going edge to a positive going edge, because I have seen clock signals go DIRECT without an inverter IC chip to a Positive edge input pin

So the Inverter IC chip must just invert the Pulse trains High and LOWs to LOW To HIGH , but what is this called when u do something like this?

The tech next to me said that there is a DELAY or phase shift on the LEADING EDGE when GATING or CLEANING up an analog signal or from a crystal, is this true?
All chips that process signals add some delay - some more than others.
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Yes true, but the crystal is an AC signal, the Smitt buffer is a GATE , so the crystals duty cycle or symmetry gets converted to a logic 50% duty cycle, so there is a phase shift or delay between the output signal of the crystal compared to the output of the smitt trigger buffer

This SMitt buffer cleans up and sharpens the Edges so they aren't rounded either right?
 

danny davis said:
Why are the edges rounded? what is causing the edges to be rounded?
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stray capacitance
What component inside the IC chip it is going to that determines which edge is active? what kind of component determines this?
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It does not matter. Are you going to be a chip designer? No? Then forget about it. Just trust the datasheet. If they say it is a positive edge triggered input, believe it, and move on.
So it's not the CLOCK signal that determines the which edge is active , it is the IC chip that is going into that determines which edge is active
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Yes.
So why does it need to invert the clock signal sometimes? and other times it doesn't need to invert the clock signal?
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As I said before, it depends on the larger function of the whole circuit.
Yes, it sharpens the edges so they are less rounded. They will always be a little bit rounded. There is no such thing as a perfectly sharp edge.
 

As I and other have said many times, you look it up in the datasheet of the chip it is going into.
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The circuits I'm troubleshooting has MIXED Logic IC chips , some of them are positive going edge and others are clocked with negative going edges

Isn't there a Small Time delays on the outputs of the IC logic chips that are clocked with positive going edge COMPARED to the IC chips that are clocked with the negative going edge? the outputs would have a small delay compared to each other right?

Because a clocks pulse width determines this delay time from leading edge to falling edge

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What is the main difference of using IC chips that are clocked to a positive going edge VS using IC chips that are clocked to a negative going edge?

What are the advantages and what are the differences?
 

Why are you asking about designing an IC circuit using ICs that were not available or are not available? Simply use the old ICs in the circuits you are fixing.
If your defective circuit uses an IC that is clocked by a positive-going edge then are you going to try finding the same kind of IC that is clocked from a negative-going edge? Why? IT WILL NOT WORK.

Do the clocked ICs in your defective circuit change themselves somehow so suddenly they are clocked from the other edge?? Do they glow in the dark too and leak beer all over the place?
 

The only systematic difference I know of is the TTL logic often has a faster negative going transition than a positive going transition. CMOS chips are quite symmetrical. However, you should not be wasting your time with such questions. Unless you are designing a brand new circuit, you should not need to consider if one type of transition is faster than the other. If the circuit you are debugging was designed properly, any delays like that were already accounted for by the designer. At your stage of learning, you are in no position to question the designer of the circuits you are debugging.
 

If your defective circuit uses an IC that is clocked by a positive-going edge then are you going to try finding the same kind of IC that is clocked from a negative-going edge? Why? IT WILL NOT WORK.
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Why won't it work? what will it do to the circuit? if a circuit is positive going edge and i put a negative going edge IC chip instead, will the timing be off?

If I put an Logic inverter on the clocks output, does this convert a positive going edge to a negative going edge? or vise versa?

EXAMPLE:

Clock Period = 100 uSeconds
Clock logic HIGH Pulse width = 20 uSeconds
Clock Logic Low pulse width = 80 uSeconds

Positive going edge will be Zero microseconds? the leading edge of the clocks pulse width
Negative going edge will be 20 microseconds? the falling edge of the clocks pulse width

EXAMPLE PLUS LOGIC INVERTER::

"The Clocks High and low states get inverted"

Clock Period = 100 uSeconds
Clock logic HIGH Pulse width = 80 uSeconds
Clock Logic Low pulse width = 20 uSeconds

Positive going edge will be 80 microseconds? the leading edge of the clocks pulse width
Negative going edge will be 100 microseconds? the falling edge of the clocks pulse width
 

danny davis said:
If I put an Logic inverter on the clocks output, does this convert a positive going edge to a negative going edge? or vise versa?
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The clocked logic will be clocked a half-cycle late and might not work properly.

Now you are showing us that you cannot understand English and do simple arithmetic.
 

The clocked logic will be clocked a half-cycle late
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What u mean by the logic being clocked a half cycle late? how so?


How is this wrong? I inverted the clock's time period , so the HIGH state and low state are inverted , so the leading edge is at 80usec. and the falling edge ends at 100useconds

What did i do wrong?
 

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