Improving noise question in OPAMP PCB

[yefj]

Hello , I have implemented a PCB based on the attached simulation file in the RAR and photo.
I have used ceramic capacitors of 100nF 1uF and 10uF for decoupling.
I tried to put vias on the ground plane to reduce noised.
photos description shown below.
based on the implementation how do you asses the noise level i got ? where could i improve to get a better result then photo 11.PNG zoomed?
Maybe my input signal (11.PNG) is too noisy?
maybe my power supply 7.5V is noisy and the decoupling is not working? (photo 13.PNG)
I only tested the first two stages ,What could be done to improve the result noisewise?
Thanks.

11.PNG is the input signal i get from the signal generator( I tried to simulate both on pure 1mv dc and sine 10mV pk-pk)
7.png LSPICE simulation
12.png : PCB TEST point of the output
13 .PNG: voltage singal of the input 7.5V from the power supply
q14.png PCB implementation of the schematics
physical_photos.zip: photos of the ceramic capacitors being used for decoupling.

 

[yefj]

Hello, I have only these three 0805 footprint for the filter between the first and second stages and maybe i can replace the resistor after the third stage after wards.

The problem is i designed the amplifyer to turn 1mV into 8mA at 1MHz BW, i need that BW for responce time.
So if i will put a filter between the stages i will kill the BW of the whole system?
Thanks.

 

[danadakk]

If filter cutoff is 10 Khz then yes, BW at 1 Mhz goes away.

What is the filter cutoff you want ? 10 Kz or 1 Mhz ?

So you have to attack the source of the noise (which one would do concurrently) first
and then decide what compromises you can live with in the BW of interest. Keep in mind
filters , depending on design,. have group delay, eg. latency, as another issue and depending
on architecture/design have overshoot (eg. transient response gremlins).

Tradeoffs, always tradeoffs.......


Regards, Dana,.