Hi ,
I download a PhD thesis from internet , the details as below:
TITLE : "Hybrid Continuous-Discrete-Time Multi-Bit Delta-Sigma A/D Converters
with Auto-Ranging Algorithm"
Author : Sergio Pesenti , EPFL 2007
Abstract
In wireless portable applications, a large part of the signal processing is
performed in the digital domain. Digital circuits show many advantages.
The power consumption and fabrication costs are low even for high levels
of complexity. A well established and highly automated design flow
allows one to benefit from the constant progress in CMOS technologies.
Moreover, digital circuits offer robust and programmable signal processing
means and need no external components. Hence, the trend in consumer
electronics is to further reduce the part of analog signal processing
in the receiver chain of wireless transceivers. Consequently, analog-todigital
converters with higher resolutions and bandwidths are constantly
required. The ultimate goal is the direct digitization of radio frequency
signals, where the conversion would be performed immediately after the
front -end amplifier.
ΔΣ-modulation-based converters have proved to be the most suitable
to achieve the required performance. Switched-capacitor implementations
have been widely used over the last two decades. However, recent publications
and books have shown that continuous-time architectures can
achieve the same performance with lower power consumption. Most designs
found throughout the literature use a single- or few-bit internal quantizer
with a high-order modulation. As a result, in order to achieve the
resolutions and bandwidths required today, the sampling frequency must
exceed 100MHz. This approach leads to non-negligible power consumption
in the clock generation. Moreover, the presence of such fast squared
signals is not suitable for a system-on-chip comprising radio frequency
receivers.
In this thesis we propose a low-power strategy relying on a large number
of internal levels rather than on a high sampling frequency or modulation
order. Besides, a hybrid continuous-discrete-time approach is used
to take advantage of the accuracy of switched-capacitor circuits and the
low power consumption of continuous-time implementation. The sensitivity
to clock jitter brought about by the continuous-time stage is reduced
by the use of a large number of levels. An auto-ranging algorithm is developed in this thesis to overcome the limitation of a large-size quantizer
under low-voltage supply. Finally, the strategy is applied to a design example
addressing typical specifications for a Bluetooth receiver with direct
conversion.