how to connect External memory to altera fpga

[barry]

my dear friend! I really sorry for your posts:-(
i have worked with MAX700s (old CPLD series) some years ago and i have enough information about CPLDs and FPGAs(either Architecture or applications), but unfortunately you imagine that youuuu know all.
my question is very clear: I have designed a hardware, and i have described it by Verilog.I have necessary information to simulate it with Modelsim, but I want to write a paper and so i had to mention a real FPGA name in my paper (note: i dont have any FPGA device so i can not use IP core as External memory). I want only do simulation on such FPGA device (I dont want to make or fabricate anything).
DO you got it? Do you have any worthful for me? If not, please stop your insulting answers.
tnx

I, along with others here, have tried to be helpful to you, but you seem to be stubbornly resistant to everyone's advice. We have asked you straight-forward questions and get vague, irrelevant answers. Yes, we all understand that you have a great, big, huge genome and need a lot of memory, but you seem unwilling to formulate a proper question. I do not imagine that I know it all, but I DO know what I don't know. That, sometimes, is even more important.

Do not worry about any further insults from me. I'm done.

 

[mrflibble]

Just curious...did you self impose the FPGA requirement or was this something that was dictated by your professor? I get the impression you don't have enough hardware experience to develop a hardware architecture for this design. Your proposed paper seems like it will be based on hand waving, as you won't be proving you can hardware accelerate anything. Without an actual hardware implementation a simulation doesn't prove anything as you can write unsynthesizable Verilog that doesn't represent a real hardware design. If you aren't targeting hardware you might as well "simulate" it using something easy like Matlab or C.

I may have emphasised a bit here and there.

But we are making assumptions based on your posts. We could be wrong, that's why some of us ask for some bits of code from your project. Sometimes a good bit of code helps communicate things a lot faster. Things like code style, interesting mixes of blocking and non-blocking assignments, novel approaches to pipelining. That sort of thing.

If all you are going to do is simulate, I have to ask: why even involve a HDL like verilog. If the end goal is to verify that a design could be configured on an actual fpga, then you will have to make your verilog code synthesizable (which is harder to do than simple simulation code). If on the other hand you are only going to simulate then you are much much better of with something like python/C++ or even matlab. And yes, even the massive parallelism of fpga's you can simulate.

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But why are you using a 5 year old version of the tool, especially when you've spoken about the Cyclone 5 (and now S4 and V) in other posts.

Presumably because that is what they have installed on the department computer. On the bright side, at least that way the inevitable use of verilog-1995 style port declarations will be more properly aligned with the tool version.