how to connect External memory to altera fpga

[barry]

which IDE do you suggest for my verilog code?

Again: What are trying to do?

 

[TrickyDicky]

which IDE do you suggest for my verilog code?

Without seeing the code, I dont know
Based on your previous comments, Im guessing it does everything in a single clock cycle, and now you think you have the answer. Id put money on the theory that you need to bin your code and start again...

 

[mrflibble]

I suggest you use Quartus as IDE. Why? Because it is what you already have, and it should get the job done. Judging by your replies choice of IDE is not the most pertinent issue.

Maybe posting some code snippets might help. Because I bet the same thing as TrickyDicky: your current version is going to be very light on the pipelining (read: none whatsoever), and very heavy on the "Looks suspiciously much like C".

 

[zarakhan]

Mmmh? When I say simulate I mean simulate inside of a simulator, not run on actual fpga hardware. You do not need to "fit your design on fpga" to be able to do a simulation. In fact, you don't even need anything fpga specific to do a simulation of this sort.

All you have to do is that stuff I already typed in the previous post.

If you don't know how, google something like "simulate memory verilog". That gives relevant hits (and hints) on how to do that. And before you grab the wrong links ... you want to do a behavioral simulation of memory. Which is good news, because that is easy. It is simulating details related to actual dram which is hard, but to be crystal clear, you do NOT need those dram details at this stage.

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Agreed. Schematic entry sucks balls (I believe that is the correct technical term for it), and relying on it now will only make you want to kick yourself at a later stage.

I am writing a paper about "FPGA-based fast pattern searching on the huge genome", so i had to use a specified fpga to prove my claims. but my problem is that i dont have such fpga that supports huge external memory (such as CYCLONE V) so i want to only simulate my project on such fpga.
I know that i cannot simulate without a first compilation, i mean i must first choose a device from "Assignments-> Devices" menu of QuartusII and then compile from "Processing_>Start compilation" menu and then i can do simulation.

On the other hand, i don't need to make a portable design, because i only need the results for my paper.

 

[TrickyDicky]

This shows you have quite severe ignorance.

You can connect plenty of memory to an FPGA. I have used systems with about 8GB connected to a single FPGA, and this was designed several years ago.

Maybe you should brush up on your knowledge.

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Maybe you should read these couple of documents:

http://www.altera.com/literature/hb/external-memory/emi_intro.pdf
http://www.altera.co.uk/literature/hb/external-memory/emi_intro_specs_select_memory.pdf

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Btw, if you compile a design, you are not simulating it - but actually running it. You may be running an emulation, rather than simulation.
Simulation refers to simulating the code on a PC based simulation program, like modelsim.

 

[mrflibble]

So this is your first fpga design is it? Don't you have fellow students in your group that have some more experience? I have viewed enough "Novel FPGA based design for DNA sequencing waffles with cream on top" papers, and an aweful lot sound pretty much like you. That being a bit light on the practical experience with digital design and such.

Because if you cannot answer the "How did you pipeline your design?" question, you are in for some learning. Well, or not too much learning combined with a total shit design, a bit depending on how you choose to allocate your time.

I point that out because fpga's do have some strong points for this particular problem, BUT they also have rather severe deficiencies compared to a hard multi-core cpu or a GPU. And getting both the pipelining and the memory access right plays a big part in making good use of the fpga's strong points.

Also case in point: if your design does not using block rams and fabric flip-flops in a clever manner it is also going to be sub-par. Then again, this is an academic paper, so if you derate it by a factor of 10 you should be okay. Normal people design: 200-400 MHz. Academic waffles with cream on top design: 20-40 MHz. That should be doable, and gives you some room to compensate for any lack of knowledge you might encounter. See, it's all about managing expectations. XD

The only drawback to all of this: Now I would really like some waffles with cream and strawberries on top. :-( Curse you, appetite, curse yooooouuuuuuu!

PS: If you only have a few months to get things done either you need to seriously pick your battles, or stock up on the caffeine.

PPS: Waffles and coffee it is!

 

[barry]

I am writing a paper about "FPGA-based fast pattern searching on the huge genome", so i had to use a specified fpga to prove my claims. but my problem is that i dont have such fpga that supports huge external memory (such as CYCLONE V) so i want to only simulate my project on such fpga.
I know that i cannot simulate without a first compilation, i mean i must first choose a device from "Assignments-> Devices" menu of QuartusII and then compile from "Processing_>Start compilation" menu and then i can do simulation.

On the other hand, i don't need to make a portable design, because i only need the results for my paper.

If you are SIMULATING then you don't need to compile. You apparently need to learn a lot more about FPGAs before you start writing papers about them.

 

[zarakhan]

If you are SIMULATING then you don't need to compile. You apparently need to learn a lot more about FPGAs before you start writing papers about them.

How???
plz clarify some more (with QuartusII). Can i simulate a project in quartus without compiling it?how?

 

[mrflibble]

Well, turned out as pancakes and coffee.

Anyways, what would good resources be for an introduction on fpga design workflow? I just realized that I don't really have a single (or two) websites on that subject. It's all bits and pieces from here and there...

Anyone know any good ones? That being good websites as introduction and maybe medior level on the subject of fpga design workflow...

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How???
plz clarify some more (with QuartusII). Can i simulate a project in quartus without compiling it?how?

Configuration settings required: brain=on
Website required: Google
Action required: "quartus simulation example" [Search]
Result: https://bit.ly/1w1GSQx

 

[zarakhan]

If you are SIMULATING then you don't need to compile. You apparently need to learn a lot more about FPGAs before you start writing papers about them.

It is not possible with QuartusII to do SIMULATION without compilation.Is it?How?

 

[ads-ee]

QuartusII uses Modelsim AE to simulate. So all you have to do is launch modelsim. Compile (Okay, build the simulation image ;-)) the code in modelsim using vlog/vcom (verilog/vhdl) commands then launch the simulation with the vsim command. You don't even need QuartusII installed except to get the modelsim AE and the quartus libraries (if you even need them)

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https://www.altera.com/literature/ug/ug_gs_msa_qii.pdf

 

[mrflibble]

Forget the word "compile" there, it's sometimes a source of confusion. Just read a tutorials on how to simulate a design, free of charge and made by the nice people at Altera. All that is required is you spending some time learning how to simulate a design. See previous link on info how to.

 

[barry]

I still question the chutzpah (look it up) of someone writing a paper about something they haven't bothered to really learn about. And I HOPE this is a paper for a college class rather than for publication.

 

[zarakhan]

I still question the chutzpah (look it up) of someone writing a paper about something they haven't bothered to really learn about. And I HOPE this is a paper for a college class rather than for publication.

my dear friend! I really sorry for your posts:-(
i have worked with MAX700s (old CPLD series) some years ago and i have enough information about CPLDs and FPGAs(either Architecture or applications), but unfortunately you imagine that youuuu know all.
my question is very clear: I have designed a hardware, and i have described it by Verilog.I have necessary information to simulate it with Modelsim, but I want to write a paper and so i had to mention a real FPGA name in my paper (note: i dont have any FPGA device so i can not use IP core as External memory). I want only do simulation on such FPGA device (I dont want to make or fabricate anything).
DO you got it? Do you have any worthful for me? If not, please stop your insulting answers.
tnx

 

[mrflibble]

Can you post some of your code? That should make it easy enough to guess what kind of help you require to solve your problem.

 

[ads-ee]

(note: i dont have any FPGA device so i can not use IP core as External memory). I want only do simulation on such FPGA device (I dont want to make or fabricate anything).
DO you got it? Do you have any worthful for me? If not, please stop your insulting answers.
tnx

Just pick an FPGA (Perhaps a Stratix IV/V, as you are using Altera) and generate the memory interface for either a DDR2/3 and get a model for a DDR2/3 part from https://www.micron.com. Instantiate the DDR interface in your code and add the DDR2/3 model to the testbench. Once you've done all that you'll have to redo your pipeline (which I hope you have one, otherwise you won't be able to write and read from the memory in any meaningful way).

If DDR2/3 latency is a problem then you can always use multiple QDR-II devices to get your 3GB of memory https://www.cypress.com/sync_srams/. Just create the memory interface using the megawizard for the QDR-II/II+ and add it to the design and get the model for it from Cypress.

FYI the answers you are getting are because you keep assuming we know what you are doing. In a forum such as this you must never assume that anyone understands your requirements. Unless you cite your requirements and what you are trying to accomplish others may jump to the wrong conclusions. Re-read your first posts and put yourself the position of not knowing anything about the application or the requirements and prove that you would be able to make the right conclusions on how knowledgeable the poster is. I sure couldn't, hence my lack of responses until much later in the thread after some real information and a specific question was posted.

 

[zarakhan]

Just pick an FPGA (Perhaps a Stratix IV/V, as you are using Altera) and generate the memory interface for either a DDR2/3 and get a model for a DDR2/3 part from https://www.micron.com. Instantiate the DDR interface in your code and add the DDR2/3 model to the testbench. Once you've done all that you'll have to redo your pipeline (which I hope you have one, otherwise you won't be able to write and read from the memory in any meaningful way).

If DDR2/3 latency is a problem then you can always use multiple QDR-II devices to get your 3GB of memory https://www.cypress.com/sync_srams/. Just create the memory interface using the megawizard for the QDR-II/II+ and add it to the design and get the model for it from Cypress.

It seems that QuartusII 9.1 dosn,t support DDR, and only have RAM and ROM in Memory Compiler.
1) do later versions support DDRs?
2) does stratix IV / V support multiple DDR?
3)is it free?
4) and you mean to make a 3Gbyte memory i must use about 1000 QDRII?!!! (an QDRII is 36MBit memory).:sad:

 

[ads-ee]

It seems that QuartusII 9.1 dosn,t support DDR, and only have RAM and ROM in Memory Compiler.
1) do later versions support DDRs?
2) does stratix IV / V support multiple DDR?
3)is it free?
4) and you mean to make a 3Gbyte memory i must use about 1000 QDRII?!!! (an QDRII is 36MBit memory).:sad:

1) yes
1a) you could just do as others have suggested and just create a behavioral memory model. If all you plan to do is simulate this (i.e. no synthesis, mapping, or place and route)
https://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
2) yes
3) yes Quartus II Web Edition (which doesn't support Stratix, but that doesn't really mater you just want to be able to generate a DDR controller core), but I don't know how big a design the free version of Modelsim AE can support.
4) well I was thinking you could use the QDRII model but modify the code (it's not encrypted) and make the ram array larger...along with adding more address bits.

If you don't really care that the design is realistic and you insist on using a hardware description language (HDL) then you should probably just go with 1a and create a behavioral memory and just make it 4GB in size. Of course any free version of Modelsim probably won't run it, or will run it 100x slower. If you know Verilog you might want to use icarus verilog on a linux box or a linux VM with access to 8GB of memory.

Regards

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You know if the design you are working on can't be implemented in an FPGA and won't be implemented in an FPGA, there is really no reason to even mention a specific FPGA in the paper. I would just say it's modeled in Verilog and would have to be modified to fit in any current generation of FPGA to utilize an external memory device.

Just curious...did you self impose the FPGA requirement or was this something that was dictated by your professor? I get the impression you don't have enough hardware experience to develop a hardware architecture for this design. Your proposed paper seems like it will be based on hand waving, as you won't be proving you can hardware accelerate anything. Without an actual hardware implementation a simulation doesn't prove anything as you can write unsynthesizable Verilog that doesn't represent a real hardware design. If you aren't targeting hardware you might as well "simulate" it using something easy like Matlab or C.

 

[TrickyDicky]

9.1 does support DDR (and Im sure some versions before that did too)
http://www.altera.co.uk/literature/ug/ug_altmemphy.pdf

But why are you using a 5 year old version of the tool, especially when you've spoken about the Cyclone 5 (and now S4 and V) in other posts.

so the asnwers are
1) Yes (and earlier ones too)
2) yes (and so do other chips - it depends how many IOs you got)
3) Why are you asking this? surely someone who wants DDR ram and is writing a paper has a budget of some kind to buy some proper tools
4) Wow.


You really need to take one MASSIVE step back - please, for the love of research!

 

[ads-ee]

9.1 does support DDR (and Im sure some versions before that did too)

Thanks for pointing this out. I couldn't remember if that version supported DDR memories. I thought it did, but couldn't remember which version I used for a Cyclone III design that had a NiosII with DDR.

You really need to take one MASSIVE step back - please, for the love of research!

This is really good advice. You should really decide if you are trying to "simulate" a potential acceleration method that could potentially be implemented in an FPGA with further research or you are implementing a hardware accelerator for DNA sequencing and are writing a paper on how it compares to traditional software only methods.