barry
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which IDE do you suggest for my verilog code?
which IDE do you suggest for my verilog code?
Mmmh? When I say simulate I mean simulate inside of a simulator, not run on actual fpga hardware. You do not need to "fit your design on fpga" to be able to do a simulation. In fact, you don't even need anything fpga specific to do a simulation of this sort.
All you have to do is that stuff I already typed in the previous post.
If you don't know how, google something like "simulate memory verilog". That gives relevant hits (and hints) on how to do that. And before you grab the wrong links ... you want to do a behavioral simulation of memory. Which is good news, because that is easy.It is simulating details related to actual dram which is hard, but to be crystal clear, you do NOT need those dram details at this stage.
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Agreed. Schematic entry sucks balls (I believe that is the correct technical term for it), and relying on it now will only make you want to kick yourself at a later stage.
I am writing a paper about "FPGA-based fast pattern searching on the huge genome", so i had to use a specified fpga to prove my claims. but my problem is that i dont have such fpga that supports huge external memory (such as CYCLONE V) so i want to only simulate my project on such fpga.
I know that i cannot simulate without a first compilation, i mean i must first choose a device from "Assignments-> Devices" menu of QuartusII and then compile from "Processing_>Start compilation" menu and then i can do simulation.
On the other hand, i don't need to make a portable design, because i only need the results for my paper.
If you are SIMULATING then you don't need to compile. You apparently need to learn a lot more about FPGAs before you start writing papers about them.
How???
plz clarify some more (with QuartusII). Can i simulate a project in quartus without compiling it?how?
It is not possible with QuartusII to do SIMULATION without compilation.Is it?How?If you are SIMULATING then you don't need to compile. You apparently need to learn a lot more about FPGAs before you start writing papers about them.
I still question the chutzpah (look it up) of someone writing a paper about something they haven't bothered to really learn about. And I HOPE this is a paper for a college class rather than for publication.
Just pick an FPGA (Perhaps a Stratix IV/V, as you are using Altera) and generate the memory interface for either a DDR2/3 and get a model for a DDR2/3 part from https://www.micron.com. Instantiate the DDR interface in your code and add the DDR2/3 model to the testbench. Once you've done all that you'll have to redo your pipeline (which I hope you have one, otherwise you won't be able to write and read from the memory in any meaningful way).(note: i dont have any FPGA device so i can not use IP core as External memory). I want only do simulation on such FPGA device (I dont want to make or fabricate anything).
DO you got it? Do you have any worthful for me? If not, please stop your insulting answers.
tnx
Just pick an FPGA (Perhaps a Stratix IV/V, as you are using Altera) and generate the memory interface for either a DDR2/3 and get a model for a DDR2/3 part from https://www.micron.com. Instantiate the DDR interface in your code and add the DDR2/3 model to the testbench. Once you've done all that you'll have to redo your pipeline (which I hope you have one, otherwise you won't be able to write and read from the memory in any meaningful way).
If DDR2/3 latency is a problem then you can always use multiple QDR-II devices to get your 3GB of memory https://www.cypress.com/sync_srams/. Just create the memory interface using the megawizard for the QDR-II/II+ and add it to the design and get the model for it from Cypress.
It seems that QuartusII 9.1 dosn,t support DDR, and only have RAM and ROM in Memory Compiler.
1) do later versions support DDRs?
2) does stratix IV / V support multiple DDR?
3)is it free?
4) and you mean to make a 3Gbyte memory i must use about 1000 QDRII?!!! (an QDRII is 36MBit memory).:sad:
Thanks for pointing this out. I couldn't remember if that version supported DDR memories. I thought it did, but couldn't remember which version I used for a Cyclone III design that had a NiosII with DDR.9.1 does support DDR (and Im sure some versions before that did too)
This is really good advice. You should really decide if you are trying to "simulate" a potential acceleration method that could potentially be implemented in an FPGA with further research or you are implementing a hardware accelerator for DNA sequencing and are writing a paper on how it compares to traditional software only methods.You really need to take one MASSIVE step back - please, for the love of research!
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