how to connect External memory to altera fpga

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zarakhan

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hi everyone.
I am doing a project with Altera FPGA that needs at least one 2Gbyte external memory.
How can i do this?
 

Buy some memory chips and then connect a bunch of lines from the FPGA to the chips.

Do you have a more specific question?

If you had expended the absolute minimum amount of effort and searched the Altera website you would have found lots of information about memory interface IP, etc. You don't even say what you are looking for: what type of memory, how fast, etc.
 

Hi mrflibble .
Please check again your link.!! It is not about memories.
 
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mrflibble said:
This training video contains some answers to your memory related issue: https://www.youtube.com/watch?v=jKpN8uEEa5c
Click to expand...

Hi mrflibble .
Please check again your link.!! It is not about memories.

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I am using Quartus9.1 and i don't want to buy IP cores.I need only do simulation and view waveforms and use timing diagrams of Quartus to compare with other implementations.
the size of external memory must be about 3Giga Byte and the speed is not so important.
 


Static? Dynamic? SDR? DDR? DDR3? QDR? RAM? ROM? FLASH? Serial? Parallel?

Much of Altera's IP is free. And if it's not free, you can still run it as an evaluation for free. Of course, you already knew this because you've actually spent some time doing some research before posting your question here.
 
I have an idea about DNA sequencing implementation with FPGA. Human genome consists of 3billion base pairs and each base can be showed with 2bits. to store this enormous data we need 1 Gbyte. on the other hand we need extra 2Gbyte memory to store Index table to search and locate the pattern against the whole genome. certainle BRAMs don't have such big space, so we must utilize external memory,I mean Parallel ROM (because the Genome is obviously clear).
 

Its amazing - after drinking win, the internet seems even more full of gibberish than normal...
 


I am pretty sure I posted the correct link.

At any rate, I will forget all preconceived notions I have about what an fpga is good at and not so good at for accelerating certain operations re: dna sequencing. Because before you know it I might assume things. What memory access patterns + memory bandwidth does you project require? Because for all I know an SPI interface and an SD card are going to be sufficient. Hell, for some cases it IS sufficient. But what the hell do I know about your new pattern matching accelerator.

So: access patterns + bandwidth?

Also: you might want to work at presenting ideas, because all I have to work on is what I already know about dna sequencing. For an audience that specializes in digital design and that isn't necessarily into bioinformatics all that much, your dna sequencing explanation is about as useful as your first post. (Translation: very vague, and requires more work on your part to explain things.)

PS: Random observation ... for prototyping this sort of thing CPU + GPU and either python or C++ is muuuuch cheaper in terms of development time. Unless of course you already have a very specific task you intend to accelerate, then by all means. But if so, you would do well to put some time into presenting this very specific task better, so you get better advice. All you tell us now is basically "I have an idea, I need some memory connected to an fpga". Well, buy a fpga dev board with dram on it. Press some free buttons in the free altera ip core generator that is free for evaluation, and off you go.
 

If I ignore the doubts raised by zarakhan's posts for a moment and just assume that he knows what he's doing, the answer is quite simple. DDR RAM is the only useful option to implement Gbyte memory capacity, it can be either interfaced by built-in hard IP of newer FPGAs (e.g. Cyclone V) or software IP. The DDR RAM hardware design is somewhat demanding, so you'll better choose a ready-made development kit.

Nothing has been said about other application requirements except for memory size.
 

hi FvM
I think I know what i am doing. there are many softwares and tools for Pattern recognition (specially for DNA sequencing or Read alignment) such as Bowtie (2009), BWA (2009) and etc. (that utilize FM-Index to fast search) all of them runs on computers that are very slow compared with FPGAs.
Some GPU based approaches have been proposed, such as MSA-CUDA(2009),GrabFast(2012),CUSHAW(2012) and etc. However these approaches runs on computers too, on the other hand we know the benefits of FPGAs shuch as speed, cost, optimal reconfigurability and.......

my problem is only that:
I have a free QuartusII web edition software and I dont have any real FPGA device. I have designed a hardware to search pattern quickly on very enormous DNA quickly, and when i want to simulate my project in quartus i had to choose a real FPGA from device list, unfortunately there is not a free devise that supports 3Giga Byte Memory (32 bit Memory, either internal or external), (only for simulation). Is it possible to simulate (only simulate) my design?
 
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There most definitely is free-evaluation memory controller IP that will support your required memory. However, if you want to simulate your memory, you'll need to get simulation models of that memory from the manufacturer.
 



Im sorry, this shows you really do not know what you are doing.
If you have some VHDL or Verilog, but cannot fit a device, it shows you really do not understand FPGAs and their limitations. As others have pointed out, you need external memory for such huge amounts of memory. External memory will have various latencies and issues to do with access times, row/column access etc, so have you designed your algorithm to cope with all the pipelining?

An FPGA in itself is NOT a solution. A well designed algorithm that works with FPGAs strengths is the solution. Where is your code? I get the feeling that you have some really badly written VHDL/Verilog. You wont be the first to write for an FPGA as if you're writing C, and you wont be the last.
 

TrickyDicky said:
An FPGA in itself is NOT a solution. A well designed algorithm that works with FPGAs strengths is the solution.
Click to expand...

Pretty much this.

Also, if you only want to simulate it, then you can decide to use purely behavioral code for the memory subsystem. As in you could pretend to have a billion zillion bytes of true random access memory with 1 cycle access time. This would give you a rather optimistic view compared to what you can expect with real components, but it will get you started faster. When it turns out your idea is crap, then at least you have not spent a lot of effort to simulate the memory part of it. If on the other hand the initial results look promising, you can spend some more time to make the memory part of the simulation more realistic. You can even use the first simulation to get a look at the memory access pattern to get some idea of how good/bad things are going to be with real DRAM modules.
 

tnx. I have examined my design with small pattern (as a query) and small nucleotide chain (as a reference) and i have confidence it works well (i save this strings in FPGA's internal memory) . i have used mixed way(verilog+schematic) to describe my hardware and simulated this with quartusII and CycloneI Fpga. but my problem arises when i want to simulate large pattern and huge nucleotide chaine (Genome), I cannot fit my design on FPGA to simulate it because i must to have a huge RAM.
Do you have any idea?
 
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I don't understand what you mean by I cannot fit my design on FPGA. If you are only simulating this design it shouldn't matter what FPGA you are using as a simulation of behavioral code is vendor agnostic. What are the steps you are using to simulate the design? It seems to me you are trying to synthesized/map/p&r (compile) the design using QuartusII.

I would also drop the mixed Verilog+schematic entry. Doing that makes your design non-portable.
 

Mmmh? When I say simulate I mean simulate inside of a simulator, not run on actual fpga hardware. You do not need to "fit your design on fpga" to be able to do a simulation. In fact, you don't even need anything fpga specific to do a simulation of this sort.

All you have to do is that stuff I already typed in the previous post.

If you don't know how, google something like "simulate memory verilog". That gives relevant hits (and hints) on how to do that. And before you grab the wrong links ... you want to do a behavioral simulation of memory. Which is good news, because that is easy. It is simulating details related to actual dram which is hard, but to be crystal clear, you do NOT need those dram details at this stage.

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ads-ee said:
I would also drop the mixed Verilog+schematic entry. Doing that makes your design non-portable.
Click to expand...

Agreed. Schematic entry sucks balls (I believe that is the correct technical term for it), and relying on it now will only make you want to kick yourself at a later stage.
 

Maybe we should step back and ask the question: What are you really trying to accomplish here?

JUST do a simulation? Then why do you even need an FPGA in the mix? There are much better ways of doing this type of thing with computer languages, matlab, IDL, etc.

Are you just trying to develop an algorithm?

Are you ultimately expecting to implement this in hardware? Fine, then you need to identify the actual memory you intend to use and get the simulation model for that (already said this).
 


which IDE do you suggest for my verilog code?
 

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