Help me solve a test on analog design

[jejeorg]

analog test

Hi,
I' d like to have your answers to a test on analog design that was submitted to me:

1- In a single stage amplifier, increasing the loading capacitor improve or not closed loop stability?
2- In a single stage amplifier, how bias current influence the gain?
3- How to reduce offset in an op amp?
4- To realize a narrow band low noise amp stage is better to use N-channel or P-channel MOS?
5- In a fully differential amp stage, the output voltage swing can higher than supply voltage?
6- How to eliminate rigth half plane zero in a miller compensated amp stage?
7- In a class AB amp stage biased with a current "Ib", how much current can be supplied to the load?
8- What is the minimun supply voltage at which a fully differential amp stage can operate? How input nodes have to be biased?

Please answer without consulting any book, as i did (and if you want, of course)

Enjoy!

jejeorg.

 

[santhoshv78]

Re: analog test

I feel u can refer to available books on opamp design.

 

[jejeorg]

Re: analog test

I know i can find all topics of all matters in the hundreds of books i have, but this was not the spirit i posted the test with. I'd like only to see how people approach those simple questions, basing on experience or way to see things.

Have a nice day!

 

[terryssw]

Re: analog test

My answer is as follows (based on my experience and knowledge, but some cannot answer):

1- In a single stage amplifier, increasing the loading capacitor improve or not closed loop stability?
Ans: stablility increases as your GBW reduces.

2- In a single stage amplifier, how bias current influence the gain?
Ans: It depends on what the bias current referred to. If bias current of diff pair increase, gm increase thus gain increase. If output transistors bias current increases, ro decrease and gain decrease. If both diff pair and output transistor use the same current (e.g. telescopic cascode), then the gain will decrease as bias current increases.

3- How to reduce offset in an op amp?
Ans: make the area of diff pair large, also increase the channel length of tail current source. Good layout techniques must be applied also.

4- To realize a narrow band low noise amp stage is better to use N-channel or P-channel MOS?
Ans: PMOS (I am not sure)

5- In a fully differential amp stage, the output voltage swing can higher than supply voltage?
Ans: Assume the transistor drain-source voltage is small compared to the supply voltage, then fully diff opamp can have output swing approaches 2*VDD. Of course actually the swing cannot reach such number depends on how you design the Veff of each transistors.

6- How to eliminate rigth half plane zero in a miller compensated amp stage?
Ans: use lead compensation (resistor + capacitor) and make R equal 1/gm of second stage. However this cancellation is not perfect and will cause pole-zero doublet problem.

7- In a class AB amp stage biased with a current "Ib", how much current can be supplied to the load?
Ans: depends on your design, it can typically deliver 10*ib to 50*ib to the load.
8- What is the minimun supply voltage at which a fully differential amp stage can operate? How input nodes have to be biased?
Ans: It depends on what kind of op-amp you are using. For very simple diff pair opamp 0.6~0.7 VDD is minimum.

 

[opamp741]

Re: analog test

My answer is as follows (based on my experience and knowledge, but some cannot answer):

1- In a single stage amplifier, increasing the loading capacitor improve or not closed loop stability?
Ans: there in no stability issue in single stage amplifier..worst case PM is more than 90 degree.

2- In a single stage amplifier, how bias current influence the gain?
Ans: In a CS there are may be three possible loads..u can put a resistance, a diode connected load or current source load..In diode connected load CS amplifier ur gain will not be affected by bias current..In resistive load increase in bias current increases gain while in current source load increase in bias current decreases gain..

3- How to reduce offset in an op amp?
Ans: 1. Remove systemmatic offset by careful designning 2. Be careful about component Matching during layout

4- To realize a narrow band low noise amp stage is better to use N-channel or P-channel MOS?
Ans: at low frequency flicker noice will be the dominant one and PMOS devices produce less flicker noise.

7- In a class AB amp stage biased with a current "Ib", how much current can be supplied to the load?
Ans: ideally there is no limit. Practically depends on ur architecture and design.

8- What is the minimun supply voltage at which a fully differential amp stage can operate? How input nodes have to be biased?
Ans: VDD>VCM+2VTH

 

[terryssw]

Re: analog test

In my knowledge, practical single-stage amplifier does really has many cases that PM < 90 degree, especially in high speed amplifier. you will always have non-dominant pole located at somewhere in the amplifier (e.g. the non-dominant pole is located at gm/Cgs of the cascode transistor for single-stage telescopic, or at mirror pole in single stage current mirror opamp). Due to the presence of non-dominant pole, the phase margin will decrease (probably smaller than 45 degree) if GBW increase while non-dominant pole doesn't increase, and thus become unstable. If there is no non-dominant pole, opamp can be designed in very high-speed (typically exceed 3-4 GHz) while nowadays fastest opamp can only have GBW around 1GHz.

 

[opamp741]

Re: analog test

My answer was for single stage CS amplifiers..I do agree that for diffamp and cascode there exist non dominant pole..