Yes it is for the current circuit. Here it is,
There is still more to add, in particular you will need some form of feedback isolation, but for the moment the upper part is your Two Switch Forward Converter. I'm just feeding it from a voltage source, VIN, set to 340V. You do not really need the input bridge rectifier and filter capacitors in place to do this and the 50Hz stuff will slow down your analysis.
In some respects it is a demonstration of how things work but the overall purpose of the model is to give you close figures about how things perform and give you the chance to 'play' without blowing things up.
The part at the bottom is, mostly, a representation of the pieces inside a UC384X,
https://focus.ti.com/lit/ds/symlink/uc3842.pdf
Going from right to left.
U1 is the internal Voltage Error Amplifier with the 2.5V reference on its non-inverting terminal. The components around it and at the input are to set the output and provide feedback compensation. D5, D6, R5 and R6 are as shown in the block diagram. It shows a 1V zener setting the maximum current limit. I have Z1 and Z2 around the amplifier which give the same effective overall limits.
My Current Limit Comparator is a Voltage Controlled Switch, S3, which produces the PWM output. That is used to reset the D-Type flip-flop, A1, which is clocked/set by the voltage source CLK and drives the Mosfets in the converter. Again I am using ideal switches for M1/M2 and add the body-source diodes.
The current sense resistor is in circuit, RSNS, and goes to the Current Limit Comparator through R7. R8 provides 'slope compensation'. Naturally this messes up the expected maximum current limit level which may or will need adjusting. C4 is for filtering the turn on spikes. It's not needed at the moment because all of my components are 'ideal'.
There are a number of application notes at the bottom of,
AC/DC and DC/DC Power Supply - PWM Controller - UC3842 - TI.com
One of which will explain the requirement for this and the theory behind it. Looks like it is this one,
https://focus.ti.com/lit/an/slua110/slua110.pdf
but feel free to read some of the others.
Regarding the compensation. When you 'know' you can get a 'close' answer by building up 'blocks' and then stringing them together. With 'slope compensation' effectively you are controlling the output filter inductor current. It is turned into a current source.
Stick with the following, hopefully the explanation flows and makes sense.
Looking on the primary side the 1R current sense resistor would have a 'gain' of 1V/A. That gets modified by R7/R8 which implement the 'slope compensation' as a voltage divider. Being careful... it is compared to the other input of the Current Limit Comparator so instead of becoming 0.66A/V it becomes 1.5A/V.
Then it goes through your transformer with a turns ratio of 5.2 to become 7.8A/V. Don't panic about the duty cycle. As suggested the primary side is actually controlling average output filter inductor current.
Now you have a current source driving the filter capacitor, with its ESR, and the load. There is proof elsewhere that with 'slope compensation' applied the bandwidth of this particular loop, it is an 'internal loop', is Fs/2.pi.D. With the Two Switch Forward Converter D is limited to 50% or 0.5 which sets that, given Fs is 100KHz, to about 32KHz. As a result you want to cross the overall loop below this frequency.
I would warn you that I'm working assuming components are 'ideal' and do not suffer from tolerances or time and temperature variations so this is all a bit 'ideal'. Ultimately you have to 'relax' the solution to take such considerations into account. For this I'm going to use the ESR zero of the output filter capacitor, CFILT.
I'm sure manufacturing technology has improved but I'm used to seeing that zero appear at about 10KHz for low ESR capacitors which is why I picked 33mR with 470u. I'm going to choose to cross the external voltage loop over at 10KHz, below the previously mentioned 32KHz.
At that point my 7.8A/V current source is, almost, effectively driving the ESR at 33mR so the gain is 0.26V/V. The last thing to consider is that the output of the UC384X amplifier has that 2R/R attenuator at its output reducing thinfs by a factor of three so adding that in the gain drops to 0.0858V/V.
I haven't done this very well, making it up as I go along, but in 'unit' terms as you go around the blocks the various A/V, V/A, V/V should end up being consistent with the final answer. Closing the loop then in order to cross over at 10KHz, unity gain, I would need a gain of 11.65 from the voltage error amplifier at that frequency.
You might see that R2 and R4 are going to give me a gain of 11 which is near enough. Otherwise the other components make things look complicated. Let's leave that alone and look at a linear model.
GL is a Voltage Controlled Current Source which is from RSNS through the power stage into and across LFILT to drive the output filter capacitor and its load. Its value is set to 7.8 as calculated. Then you get the filter capacitor with its ESR and the load.
R5/R6 is the attenuator at the output of the UC384X voltage error amplifier and the error amplifier is U1 loaded up with the compensation components. There is an AC voltage source inserted in the loop, V1, and this allows you to measure the loop gain, and phase.
I don't want to overload the 'board' with pictures... Or I am being lazy. If I remove R1 and C3 and then short C1 and C2... Blerg. I'll put the pictures in..
Run the AC analysis and plot V(a)/V(b). This gives the loop gain as,
You get, if you expect it, a first order slope, -20dB/Decade with phase dropping to 90 degrees, up to the 3dB point at 10KHz before it flattens to 0dB. This is a current source driving a capacitor and then transitioning to driving a resistor. At low frequencies you have the current source driving the load resistance. At low and high frequencies the phase is 180 degrees which comes from the inverting amplifier.
I should not mention PID but the above would be the P or Proportional part of your loop.
With a DC path around the error amplifier then the circuit is not going to give you the output voltage you require so you break that path with C2,
The loop gain becomes,
Now you get more gain at lower frequencies but the purpose was to break the DC path around the error amplifier so it's output voltage does not interfere with the absolute level you wish to set at its input. Otherwise you will see that, ignoring low and high frequencies, the gain slope has become 40dB/Decade with the phase dropping towards 0 degrees. This is now second order.
You have an integrator, the power stage current source driving the output capacitor, followed by another integrator, the error amplifier driving C2, over that mid frequency range. The power stage integrator gets 'cancelled' by the capacitor ESR at 10KHz and I have chosen to cancel the error amplifier integrator at about 5KHz. 1/2.pi.C2.R4
Wet, experienced [not sure if I can claim that] finger in the air. Otherwise in PID terms C2 introduces the I or Integrator term into your feedback, or rather error amplifier part of it, loop.
Now we have to put R1 and C1 back in again, or maybe we don't and that might depend. With a second order section within the loop and phase dropping close to 0 degrees there is a chance that should, for some reason, the overall gain within the system fall then crossover will happen with insufficient 'phase margin' and things will ring a lot or just go unstable.
At the moment, with my 10K feedback resistor, R2, and 13K 'setting' resistor the output voltage will be dribbling along at about 4.5 volts. That is not important. I can see myself losing it myself.. I'll put R1 and C1 back in,
This improves the low frequency phase margin such that the circuit will be more tolerant of gain variations from the components used. This time I have chosen a corner frequency of 10KHz.
In PID terms this would be the D or Differentiator part of things. One of its effect is to slow rise time at start up. A rapidly changing output voltage such as that which might occur at start up gets 'stomped on'.
The last part is C3.
Whilst the linear model remains flat above 10KHz as suggested the switching model, 'real circuit' is going to 'run out of steam' at about 32KHz. In this case C3 is really there there for noise filtering and I have set it to give a 'pole' with R4 at approximately that frequency.
Match Models and 'shoot'.. Having a fiddle with output setting resistors. Being an old bloke I do not remember all the new funny resistor values so I'll add a parallel one. Whatever.
Linear model becomes,
Start up is,
0.5A to 1.5A transient performance is,
Switching model becomes,
Not much different. Now I 'cheat'.. The start up is,
It is not as 'fast' to get there as the linear model because during start up part of the time is taken up with the circuit being in primary side maximum current limit.
0.5A to 1.5A transient performance is.. I'll put these side by side for comparison. Switching model on the left linear model on the right.
Genome.