flyback transformer noise

[tictac]

Hi
I was checking my flyback simulation with LTSpice.it worked and I have 1250 volt with 35k load. but I realized that at the gate with 22 ohm resistor I have a square wave form with Imax= 330 mA .but maximum output current of 3844 is 200mA. is it better to use one mosfet driver?

regards

 

[FvM]

The gate curent waveform is not a square wave. It's zero most of the time with short spikes when switching on or off. The 3844
is able to drive it, it can be operated even without a gate resistor, according to the datasheet. I the gate current will be limited by the
3844 output stage in this case. But a gate resistor is recommended to reduce a risk of self oscillation. Using a driver with higher
current capability, e.g. TC427, can be expected to reduce the switching time and thus the switching losses by some amount, but
I guess, not considerably.

Regarding diode series circuit and balancing resistors, I would count on self-balancing by the diode capacitance and a soft
breakdown characteristic, that acts in the same manner.

 

[tictac]

yesterday I wind a new transformer with this specifications
Np=5 , Ns=390
Lp=14 uH EI-50/40
with 0.4 mm gap

at first steps of output voltage (300 v) the peak current was 16 amp. and it cant goes up to 500 volt . the source waveform of mosfet goes up to 1 volt when the output voltage was 500 volts. I think it goes to saturation mode.
when I increase the gap it goes up to 800 volt.

is it true? wehn primary turns goes down then Bmax goes upper?

if it is true so, I should better consider Np=7 so Bmax goes down and the output voltage goes upper.


I test these ways to :
1-getting 50 watt at output.
2- stopping the mosfet get hot.

is it good idea?

regards

Added after 1 seconds:

yesterday I wind a new transformer with this specifications
Np=5 , Ns=390
Lp=14 uH EI-50/40
with 0.4 mm gap

at first steps of output voltage (300 v) the peak current was 16 amp. and it cant goes up to 500 volt . the source waveform of mosfet goes up to 1 volt when the output voltage was 500 volts. I think it goes to saturation mode.
when I increase the gap it goes up to 800 volt.

is it true? wehn primary turns goes down then Bmax goes upper?

if it is true so, I should better consider Np=7 so Bmax goes down and the output voltage goes upper.


I test these ways to :
1-getting 50 watt at output.
2- stopping the mosfet get hot.

is it good idea?

regards

 

[FvM]

As previously mentioned, I was under the impression, that the windings ratio should be rather reduced, respectively the number
of primary turns increased. But the power transistor's voltage rating may be contradicting. But I fear, I have to restrict myself from
telling design recipes, as long as I don't fully understand all aspects of your circuit's behaviour.

 

[tictac]

As previously mentioned, I was under the impression, that the windings ratio should be rather reduced, respectively the number
of primary turns increased

can you describe it more,please? now I reduce primary turns to 5.

do you mean that I increase primary turn?
or do you mean that Np=5 and Ns=300(for example)?

I only want to get 50 watt power with normal temperature of mosfet .I think it related to transformer construction.Is it true?

and after it I must solve oscillation of feedback.


can you ask me about of what you want to know about my smps,please?

regards

 

[FvM]

I thought about more primary turns, not less.

can you ask me about of what you want to know about my smps,please?

It's not a primarly a problem of asking the right questions. The problems can be identified by measurements. It's e.g. possible to see
the MOSFET losses from simultaneous current and voltage measurements and determine in which phase of switch cycle they are
generated. But I'm not sure, if your measurement equipment can give the results clearly enough.

 

[tictac]

I thought about more primary turns, not less.

As the above calculation shows (DCM) for getting 70 watt power at input stage .

Lp=14 uH , Ipk=13.8 Amp.

consider constant Bmax=150 mT

with Np=10 the gap size must be larger for getting Lp=14 uH (I)
with Np=5 the gap size must be lower for getting Lp=14 uH (II)

in State I it can produce Pout=42 watt but mosfet get so hot

in state II because of lower gap the transformer goes to saturation because of more Bmax needed. If I increase the gap so the Lp decreases. for example I increase gap and Lp=7uH but the output voltage goes upper just 100 volt.

So I decide to increase Np=7 . is it good? if for example Np=14 so it need very little gap so it maybe goes to saturation. but if I consider Lp>14 with Np>10 I goes to CCM mode. is it true?

I have a 2 channel scope . I can send Vds ,Vgate, Isource, Igate waveforms.

regards

Added after 1 hours 3 minutes:

possible to see
the MOSFET losses from simultaneous current and voltage measurements and determine in which phase of switch cycle they are
generated

do you mean soft switching? I see in many smps with 3844 that there is no special circuit for avoiding losses from simultaneous current and voltage. but in some circuit there is one extra diode and resistor at gate path for adjusting the mosfet on and off time.

 

[tictac]

I have a 2 channel scope . I can send Vds ,Vgate, Isource, Igate waveforms.

possible to see the MOSFET losses from simultaneous current and voltage measurements and determine in which phase of switch cycle they are
generated

do you mean soft switching? I see in many smps with 3844 that there is no special circuit for avoiding losses from simultaneous current and voltage. but in some circuit there is one extra diode and resistor at gate path for adjusting the mosfet on and off time.

regards

 

[FvM]

I didn't imagine to modify the gate drive waveform, I just want to understand the exact reason for the transistor losses. Slowing down
the gate drive must be expected to increase the switching losses, so it's not recommended in this case. Recording Vds and Id
(respectively the current sense resistor voltage) can visualize the switching behaviour.

Regarding transformer dimensionining, I understand that Np=10 was the original design and achieved up to 1000 V (loaded) output,
but only 800 V with Np=5?

My basic idea was to increase the primary on-time to reduce the peak current. The operation wouldn't necessarily be restricted to DCM.

 

[tictac]

now I reduce the current sense resistor value to 0.03 ohm. and I test it with Np=10,Ns=620
finally voltage goes to 1300 volt with RL=35k

with Np=5 the voltage goes up to 500 volt only.

I thought that the problem was transformer and it goes to saturation and doesnt let the voltage goes up to 1300 volt.

but the mosfet is still so hot.

I think that , the Lp can be higher than this. for example 50 uH. with this value or higher Ipk will be lower and it is good for mosfet. but does it produce 70 watt power ?

regards

 

[tictac]

Regarding transformer dimensionining, I understand that Np=10 was the original design and achieved up to 1000 V (loaded) output,

can you tell me that how do you get Np=10 ?

what is the value of Lp with Np=10?

if Lp>14 uH so it goes to CCM. is it true? maybe there isnt any choice except CCM .

can you give me the link about flyback CCM calculation,please ?


regards.

 

[FvM]

can you tell me that how do you get Np=10 ?

I referred to your post of 07.04., where you reported this value. The schematic tells Np=9 in contrast.

what is the value of Lp with Np=10?

I don't know. How did you choose the air gap til now? I also didn't understand, if the L values given in your previous posts have
been measured or are only design target values? I have no special literature about CCM. I'm simply under the inpression,
that it would be good to have a higher primary duty cycle and lower peak current to reduce the transistor stress, and hopefully
losses, too. I think, Lp of 40 or 50 uH won't be bad.

 

[tictac]

I also didn't understand, if the L values given in your previous posts have
been measured or are only design target values

yes. I measure all of value with LC meter and they are precise.

with Lp=40uh it goes to ccm . and as I know it is very difficult that remove feedback oscillation in this mode , specially its output voltage changes in wide range.is it true?
whats the solution?
regards.

 

[FvM]

CCM has the special problem with current mode control, as previously discussed. It needs slope compensation. But apart from this,
the converter gain is less current dependant in CCM, if I understand right. Most PWM controllers work fine in CCM.