This evaluation filter circuit is a filter design used to block microwave power signals from feeding back into the DC source, from the amplifier RF out connected to an external RF load (e.g. some Radar RF power port.)
The filter uses inductors (L1, L2, L3) are low Z near DC and high Z at RF defined as "parasitic components such as parasitic capacitance (Cp) and DC resistance (DCR).
The Capacitors may be std LF or RF ceramic NP0/C0G types , which have the lowest ESR and ESL parasitics too. But if you are talking about 10GHz+ RF these cannot be ignored.
Any significant change in component values affects the spectral impedance and attenuation in both directions.
These dual direction attenuations may be computed by scattering (s) parameters or S-parms. or s11, s12, s21, s22.
Key points include:
- The filter allows low-loss DC to pass while blocking RF signals from reflecting into the DC source.
- The design ensures high return loss (high RF signal loss) into the DC source, providing high impedance to RF.
- The filter’s behavior and performance are influenced by parasitics, and design choices must consider impedance effects within the bandwidth of the DC voltage regulator.
Above all, every Gnd symbol on the schematic must be 0 V +/- ?? tolerance for noise from DC to > 10GHz. This tolerance is defined by the perturbation limits of s-parms and the EMC interference levels of the Device Under Test (DUT) for both emissions and susceptibility. **
Anecdotal
I recall a large 14" disk drive near the top floor of the tallest building in Winnipeg, in the heart of the financial district was getting random soft and hard errors. It was later found to be caused by the 1kHz pulsing of RF from the airport Radar as its antenna was rotating when synchronized with a data read/write in sync along with other events. Improved shielding/grounding of the R/W RF signal path was the fix.