fixing design for simultanios excitation of a sequencer

[yefj]

Hello,The circuit is supposed to delay the output of P12 because the PNP is opening gradually.
In previos version it worked great but i put P12 as a pulse and circuit just not working.
The Veb is totally different.Veb is supposed to be 0 and rise gradually.
But when i made P12 0-12V pulse my Veb is tottaly ruined.
How can i fix it so Veb will rise gradually from 0 till PNP is opening?
LTSPICE file is attached.
Thanks.

 

[yefj]

UPDATE:
Hello , What about the situation when i move C4 to be parralel to R10.
There is a basic law regarding capacitors shown below.
"The principle of continuity of capacitive voltage says: In the absence of infinite current, the voltage across a capacitor cannot change instantaneously."

looking at the following situation how does the capacitor acts?
one leg feel rise of zero to 12V what does the other leg get because of that and why?

 

[BradtheRad]

Hello Brad , So in the original case C4 was directly charged by P12 and it charges very fast.
In the upgraded version there is no pass to the ground from the base .
What what is physically happening to the capacitor
We have a capacitor in parallel to R10, a pulse is coming .
How it will react? It will start charging .
What is the difference of charging in the first and second case?
When pulse comes Veb is not 12 automatically .
why in the second case C4 is charged slower?
Thanks .

C4 now charges and/or discharges through the resistor network... an RC time constant can come into play.

C4 now succeeds in holding Q1 Off at power-up, because it conveys positive voltage to the PNP's base. The situation changes as C4 charges.

 

[yefj]

Hello Brad,As you can see below C4 charge current is much much less then sitatuon 1.
Can you see the logic in the current plot ?
at first the current rises to 20mA then at some point there is a very sharp drop in the current exacrly then the base voltage starts to be 11.2V.
What causes this current behavior?
"C4 now succeeds in holding Q1 Off at power-up, because it conveys positive voltage to the PNP's base. The situation changes as C4 charges."
LTspice file is attached.
situation 2:

 

[D.A.(Tony)Stewart]

Several design flaws:

1. No design specs for tolerances Tr, Tf on P21 nor Td +/- , Tr, Tf, & Iout.
2. No R series controlled current limit on Veb of Q2. Power on applies >10V across Veb on start.
3. No protection of Veb from excessive reverse voltage{>-5V} from contact bounce if any (?)
4. There is no current limiting series R other than PNP-Reb + ESR (C4)

--- Updated Today at 1:35 PM ---

Also in spite of occasional datasheet flaws. [nS] is nano-Siemens, while [ns] is the only correct abbreviation for nanosecond.

Simultaneous ends in “ous”

 

[BradtheRad]

Can you see the logic in the current plot ?
at first the current rises to 20mA then at some point there is a very sharp drop in the current exacrly then the base voltage starts to be 11.2V.

The principle underlying all this revising... is the behavior of a PNP. Textbooks cheerfully tell us it's the opposite of NPN. However PNP is less familiar, less intuitive. The polarities and bias method require a different format when operating a PNP.

Likewise the technique of putting a time-delay capacitor in the bias wire. You're gravitating toward the correct arrangement although there's still more optimizing to be done. Adding a resistor here, removing (or altering) a resistor there.