fixing design for simultanios excitation of a sequencer

[yefj]

Hello,The circuit is supposed to delay the output of P12 because the PNP is opening gradually.
In previos version it worked great but i put P12 as a pulse and circuit just not working.
The Veb is totally different.Veb is supposed to be 0 and rise gradually.
But when i made P12 0-12V pulse my Veb is tottaly ruined.
How can i fix it so Veb will rise gradually from 0 till PNP is opening?
LTSPICE file is attached.
Thanks.

 

[D.A.(Tony)Stewart]

The criteria for the supply filter is the attenuation greater than 6.02 dB or phase shift in the signal BW.

I assume a matched load to source impedance = 6.02 dB.
Modify my assumptions to your design.

Parasitic inductance should be included with an estimate of ESL=0.5~0.6 (?) [nH/mm] for short traces and ln(l/w) ratio.

 

[yefj]

Hello, So basickly its a filter to pass the pulse to the amplifier
In Ltspice I have made equivalent circuit with AC transfer function response with 5Mhz BW 69Mhz.
the original circuit acts good but as you can see in the last photo When i lowered the 1.1uH to 100nH an the pulse goes threw much better.
One dilemma I have regarding the load.I will connect this circuit to spectrum analyzer.
What load do i need to put in the simulation to test the response?
Thanks.
https://www.rfwireless-world.com/calculators/Rise-Time-to-Bandwidth-Calculator.html