fixing design for simultanios excitation of a sequencer

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yefj

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Hello,The circuit is supposed to delay the output of P12 because the PNP is opening gradually.
In previos version it worked great but i put P12 as a pulse and circuit just not working.
The Veb is totally different.Veb is supposed to be 0 and rise gradually.
But when i made P12 0-12V pulse my Veb is tottaly ruined.
How can i fix it so Veb will rise gradually from 0 till PNP is opening?
LTSPICE file is attached.
Thanks.
 

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UPDATE:
Hello , What about the situation when i move C4 to be parralel to R10.
There is a basic law regarding capacitors shown below.
"The principle of continuity of capacitive voltage says: In the absence of infinite current, the voltage across a capacitor cannot change instantaneously."

looking at the following situation how does the capacitor acts?
one leg feel rise of zero to 12V what does the other leg get because of that and why?
 

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C4 now charges and/or discharges through the resistor network... an RC time constant can come into play.

C4 now succeeds in holding Q1 Off at power-up, because it conveys positive voltage to the PNP's base. The situation changes as C4 charges.
 

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Hello Brad,As you can see below C4 charge current is much much less then sitatuon 1.
Can you see the logic in the current plot ?
at first the current rises to 20mA then at some point there is a very sharp drop in the current exacrly then the base voltage starts to be 11.2V.
What causes this current behavior?
"C4 now succeeds in holding Q1 Off at power-up, because it conveys positive voltage to the PNP's base. The situation changes as C4 charges."
LTspice file is attached.
situation 2:



 

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Several design flaws:

1. No design specs for tolerances Tr, Tf on P21 nor Td +/- , Tr, Tf, & Iout.
2. No R series controlled current limit on Veb of Q2. Power on applies >10V across Veb on start.
3. No protection of Veb from excessive reverse voltage{>-5V} from contact bounce if any (?)
4. There is no current limiting series R other than PNP-Reb + ESR (C4)
--- Updated ---

Also in spite of occasional datasheet flaws. [nS] is nano-Siemens, while [ns] is the only correct abbreviation for nanosecond.

Simultaneous ends in “ous”
 
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yefj said:
Can you see the logic in the current plot ?
at first the current rises to 20mA then at some point there is a very sharp drop in the current exacrly then the base voltage starts to be 11.2V.
Click to expand...
The principle underlying all this revising... is the behavior of a PNP. Textbooks cheerfully tell us it's the opposite of NPN. However PNP is less familiar, less intuitive. The polarities and bias method require a different format when operating a PNP.

Likewise the technique of putting a time-delay capacitor in the bias wire. You're gravitating toward the correct arrangement although there's still more optimizing to be done. Adding a resistor here, removing (or altering) a resistor there.
 

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Hello Brad, My main concern is with the reference voltage components.
For example if I need to supply -2.5V and maximum 4.5mA then my tl431 can supply much more.
How can i make sure it wont supply more current then the load device can handle?
Thanks.
 

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yefj said:
Hello Brad, My main concern is with the reference voltage components.
For example if I need to supply -2.5V and maximum 4.5mA then my tl431 can supply much more.
How can i make sure it wont supply more current then the load device can handle?
Thanks.
Click to expand...
The startup sequence tells you to start with a certain negative supply (-2V or -2.5V), then adjust it to obtain the Amperes you desire. While experimenting you must hook up instruments that tell you what's going on. No one can predict exactly how your power amplifier module will behave. It's true the TL431 might send more current than is healthy for your system. Any power supply is capable of doing such a thing if you adjust its voltage off-spec. That's why you must watch carefully as you start the system operating.

There's a chance you can make crude adjustments of the transistor and bias network so that it tends to limit current within an acceptable range. Even if you install a current-limiting circuit, you'll still spend a lot of effort watching values and turning a potentiometer.
 

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Hello Brad,What LAB startegy do you reccomend to monitor the current situation ?
I assume after the -2.5V will set on the Vg1 gate i will have constant current flowin into the Vg1.
What is the way used in labs to monitor the current preventing for the aplifier to burn?
You mentioned a current limiting circuit and potentiometer.
Do i need to add a current limitin circuit? I already have a current limiting resistor R^ shown below.
Could you be more specific what current limiting circuit i could use?
Where do i put the potentiometer?
WHat is the general way you work with them?
Thanks.

 
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I measure volts across the device (or pins of the device). A DMM is suitable.

My meter leads have attachable alligator clips purchased at Radio Shack.

To measure Amperes I install a second meter inline. DMM may be suitable but not always. I often use my old-fashioned VOM, first on the 300 or 500 mA range. If the reading is tiny then I switch to a smaller range. The smaller ranges insert a resistance in the circuit. Sometimes that resistance affects circuit operation.

Inside DMM's I've seen a 200mA fuse for Ampere ranges other than 10A. More than once it needed replacing after exposure to greater current. For another thing, a DMM only updates its reading a few times per second. However the moving-needle type makes it easy to spot a trend upward or downward.
 

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Hello Brad, regarding Layout /LAB considerations :
1.I plan to create the plus 12 and -12V by purely pluging a 3 pin molex into a power supply and pressing the power on button,this is the pulse .I was told that using TL431 with negative power supply voltage need special layout for the negative power supply.If its true could you say what needs to be done?
2.Where in the circuit you reccomend to put decoupling capacitors?
Thanks.
 

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"Simultaneous excitation of a sequencer can lead to unpredictable behavior. To prevent this, consider using a gated clock or adding additional logic to ensure that only one input is active at a time. Are you working with a specific type of sequencer or design tool?"
 

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yefj said:
TL431 with negative power supply voltage need special layout for the negative power supply.If its true could you say what needs to be done?
2.Where in the circuit you reccomend to put decoupling capacitors?
Click to expand...
Schematics make C terminal voltage more positive than A terminal. Does it matter which wire has the safety resistance? That's the big question. This arrangement yields the proper regulated voltage though it's not the conventional method to use TL431.

Advice says put capacitors where they smooth voltage in spots where volt level easily gets jittery. Example, close to power supply terminals to IC's.

 

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Hello Brad, I have started to build the PCB.one dilema I have regarding the capacitors at the ports of the amplifier.In the datasheet they asume we switch voltage sequence manually.
But in our case we have built a sequencer.
How in real life lab you reccomend me to see if i need load capacitors at Vg1 Vg2 Vdd?
 

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yefj said:
regarding the capacitors at the ports of the amplifier.In the datasheet they asume we switch voltage sequence manually.
But in our case we have built a sequencer.
How in real life lab you reccomend me to see if i need load capacitors at Vg1 Vg2 Vdd?
Click to expand...
I believe the numerous capacitors are different values and different types, recommended as a 'good idea' on supply rails close to a sensitive device. Known as decoupling or bypass capacitors. Stabilize the DC power source.

Not every type or value does an equal job filtering out a given frequency of noise and spikes. Therefore designers usually mix various small Farad values, covering various ranges and types.
 

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You need to breakdown these requirements into discrete steps checking for voltage errors at each step and if any error condition occurs drop Vg2 to -5V to cutoff any possible Id and thus cut Pd. This can include exceeding the Absolute Maximas and allowed tolerance for regulation error in a discrete step sequence for RF ON and OFF sequences. Then define these states then design it. So far no one has done this, but this is your task. Pls reset all queries and try again now.
--- Updated ---

I suggest you review the recommended circuit
 
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To avoid design/Assy failures on 1st evaluation of the $1200 RF FET board on Roger’s substrate with proper thermal attachment with wire bond connections and regulated control board ~$250 approx will achieve better use of your time to evaluate the design recommended by Qorvo starting at 5 to 8V for Vdd allowing increase to 12 or 15V when confident results are achieved.
Quantum-X Microwave has a lower cost eval kit about half the price.
https://www.mouser.com/images/marketingid/2024/img/135793161.png?v=070924.1056 From Mouser.

I don’t think you are ready to roll your own yet.
 
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Hello Brad,A more important point is regarding the VDD.
We have +12V pulse coming to bias the RF output.
I know that all of these inductors are basickly RF chokes so the RF signal wont go to the Vdd port.
How can I know in simulation (LTspice) or in real life that I have a good RF isolation from the Vdd port?
How they got to the values and structure shown in the red arrow?
Thanks.

 

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Regarding VDD I have a hunch the schematic presents a sort of composite of filtering methods. It looks like you have an option to fill in the blanks with suitable L & C values, depending on what appears on that wire.
--- Updated ---

I believe R1 provides damping in case LC oscillations get out of hand.
 

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