Fast switching transistor with slow rise/fall times, why?

[righteous]

Gentlemen,

It is my objective to put as much current in the least amount of time possible through R5. However I'm experiencing rise and fall times of Q2 are anything but appropriate for a transistor like Q2, and due to my limited experience with analog design I'm finding it difficult to debug.

Here is my circuit, and DC calculations are courtesy of partsim.com:


The V1 period is 100uS and pulse is 50ns rise, 50ns width, 50ns fall, Here is the simulated transient analysis where ORANGE is left side of R4, and RED is base of Q2, and BLUE is collector of Q2:


Any ideas/suggestion are highly welcome.

 

[zuisti]

This is an almost impossible "mission", the input pulse is too short.
And ..you know the usual rule:
the transistor (used as a fast switch) should not be driven into the saturation range ...

 

[righteous]

This is an almost impossible "mission", the input pulse is too short.

Sorry for my confusion, what do you mean by "too short"? If you mean it's too short for my specific circuit, I'm more than happy to look into an other solution.

And ..you know the usual rule:
the transistor (used as a fast switch) should not be driven into the saturation range ...

I guess someone told me that 30 years ago, but I had happily forgotten it. Thank you for the reminder ;-)

 

[FvM]

The slow rise time is observed due to unsuitable circuit, the fall time doesn't look bad for the used transistors, I think.

 

[CataM]

A speed up capacitor at the base of both transistors will certainly help.

 

[Ata_sa16]

How you have no current passing through R3. If you check, your voltage drop on R3 is 0 !!

There should a problem here. Check the current for your transistors, they seem to be off !

 

[FvM]

The circuit annotation is partly confusing, but I see a 0.7 V R3 voltage drop indicated. That's apparently too low to turn Q3 on fast enough.

Q3 is finally even saturated (Vce < Vbe), but it takes 200 ns. There are two options
- staying with saturated switching, speeding it up by appropriate means
- redesign the circuit for non-saturated switching, accepting higher voltage drops and power dissipation

 

[E-design]

Here is a switching circuit that may meet your specifications. It has some speed-up elements to enable fast switching. It uses commonly available transistors. I can't guarantee how it will perform with the transistors in your circuit. Not bench tested!

 

[righteous]

Gents,

I would like to thank everyone for their valuable input so far. I was suggested to me to insert a push/pull pair of transistors between the two existing transistors, as the slow rise/fall times could be attributed to capacitance of the junctions. Here is the revised circuit and transient analysis. Now I have to build and test it.

 

[righteous]

Here is a switching circuit that may meet your specifications. It has some speed-up elements to enable fast switching. It uses commonly available transistors. I can't guarantee how it will perform with the transistors in your circuit. Not bench tested!

Dear Mr. E-design,

Thank you for valuable proposal, the LC looks interesting (black magic) to me, I will definitely give it a try and let you know.

 

[CataM]

@post #8: The 470 nH is the parasitic ESL of the cap ? Because if not, I do not see its need.
Using C2=100 pF and no inductance switches faster than 68 pF + 470 nH inductance. Not a lot faster, but faster.

Used Tina TI 9, measured from ~0 V to 10 V, the rise time gives this:
68pF + 470 nH --> tr=4.67 ns
100pF with no inductance --> tr=4 ns

 

[E-design]

@post #8: The 470 nH is the parasitic ESL of the cap ? Because if not, I do not see its need.
Using C2=100 pF and no inductance switches faster than 68 pF + 470 nH inductance. Not a lot faster, but faster.

You are correct, but adding the inductor was for a reason. I wasn't happy with the pulse-width error that was present using only a capacitor to aid with speed-up. It can be seen on the plot it reduces the overall width error by about 1.5nS on the rising edge and 4.4nS on the falling edge. So, this combination gave me the best switching speed with the least amount of pulse-width error. It may be an overkill for this specific application.

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Using a 2N3904 and 2N3906 instead, seems to give even better speeds, resulting in tr ~ 4nS and tf ~ 3nS.

 

[E-design]

Gents,

Here is the revised circuit and transient analysis. Now I have to build and test it.
View attachment 142930

View attachment 142931

Keep us posted on the results, since I have some doubts about the performance of your circuit.

Do you have the specs on Q2?

 

[righteous]

Keep us posted on the results, since I have some doubts about the performance of your circuit.

Do you have the specs on Q2?

Absolutely. Maybe I was a bit premature on the "Solved" trigger (?)

Here's the Q2 datasheet NSS40300MZ4

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And here are the simulation models for NSS40300MZ4

 

[FvM]

Obviously using a medium current transistor with respective higher capacitances and lower ft has some impact on the switching speed. Question is why you are using it and presumed there's a reason, is the performance loss still acceptable?

 

[righteous]

Obviously using a medium current transistor with respective higher capacitances and lower ft has some impact on the switching speed. Question is why you are using it and presumed there's a reason, is the performance loss still acceptable?

The reason for using it requires a long explanation that is obsolete, so let's say I'm urinating with the equipment at hand (pun intended), but subsequently I sold my soul to Farnell, so if there are better options I'm all ears.

 

[righteous]

Keep us posted on the results, since I have some doubts about the performance of your circuit.

I built it, and you are right, it performs nothing like the sim, it sux. For starters I can't get Q1 to open unless I change R1 to 22R, and R3 to 470R, and so on... nothing get through to Q2. Not worth the time. I'll try your proposal now.

- - - Updated - - -

Here is a switching circuit that may meet your specifications. It has some speed-up elements to enable fast switching. It uses commonly available transistors. I can't guarantee how it will perform with the transistors in your circuit. Not bench tested!

I recreated your circuit in partsim.com, it didn't look exactly like your sim, so I tweaked it a bit and changed R6 to 220R and C2 to 47pF, then it looks more like your sim and I even managed to shave ~20ns off the pulse width. Now I have to see what I can do about sourcing some suitable transistors and build it.


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update for #17

As you proposed, Using a 2N3904 and 2N3906 instead, seems to shave another ~20ns of the pulse width too.


Now my concern is that 2N3906 can't handle the currents that I have planned for next iteration, and which was a reason to use NSS40300MZ4. I would like that T2 could handle 2> amps during 'on' period, could you possible suggest a suitable candidate? Or could I use two (or more) 2N3906 in 'parallel' like below, or does that constitute an electronic faux pas? (I'm asking out of ignorance)

 

[CataM]

I recreated your circuit in partsim.com, it didn't look exactly like your sim, so I tweaked it a bit and changed R6 to 220R and C2 to 47pF, then it looks more like your sim and I even managed to shave ~20ns off the pulse width.

R6 has next to nothing of a role in the switching characteristic. 220 ohms gives around 3mA of quiescent current.. a bit too much for a pull down resistor.

Now my concern is that 2N3906 can't handle the currents that I have planned for next iteration, and which was a reason to use NSS40300MZ4. I would like that T2 could handle 2> amps during 'on' period, could you possible suggest a suitable candidate?

The bipolar technology is not very suitable for high speed and high power applications. As it was already mentioned, as you go up in power, the capacitances and transition frequency increase and decrease respectively, affecting the switching performance.

Or could I use two (or more) 2N3906 in 'parallel' like below, or does that constitute an electronic faux pas? (I'm asking out of ignorance)

The negative temperature coefficient of the PNP BJT transistor makes it unsuitable for parallelizing unless additional protective means is implemented e.g. negative feedback via a resistor in the collector of each transistor.
In other words, as the temperature of the transistor goes up, the emitter-collector drop goes down, making one single transistor to hog all the current leaving the others with nothing.

 

[righteous]

R6 has next to nothing of a role in the switching characteristic. 220 ohms gives around 3mA of quiescent current.. a bit too much for a pull down resistor.

Noted.

The bipolar technology is not very suitable for high speed and high power applications. As it was already mentioned, as you go up in power, the capacitances and transition frequency increase and decrease respectively, affecting the switching performance.

Ok then I'll bite the bullet and continue with BJT and accept some minor decrease in switching performance. FET's don't seem to be able to do what I want, as I would need one without built-in fly-back diode and a RDS(on) < 1Ω at the operating voltages indicated. Below is what I came up with, fiddling around with Mr. E-design's proposal.

But now I'm concerned about the relative excessive current going through R3, can it be improved without affecting the switching further?

At the same time I note that base of Q1 (black) goes negative in the sim, would that indicate that the circuit would not work as sim'ed? Or is there another reason for the negative peak?

The negative temperature coefficient of the PNP BJT transistor makes it unsuitable for parallelizing unless additional protective means is implemented e.g. negative feedback via a resistor in the collector of each transistor. In other words, as the temperature of the transistor goes up, the emitter-collector drop goes down, making one single transistor to hog all the current leaving the others with nothing.

Noted, I recall now hearing something along those lines in my earlier days.

 

[CataM]

At the same time I note that base of Q1 (black) goes negative in the sim, would that indicate that the circuit would not work as sim'ed? Or is there another reason for the negative peak?

No. The negative current means that it is pulling out charge from the base, turning it off faster. The peak negative current is higher with respect to the current you would notice if there was no speed-up capacitor at the base. You need to remove the charge from the base emitter junction before the current goes to 0, just like the reverse recovery of a diode.