Digital oscilloscope Project

[wassa]

jyetech oscilliscope

i want to ask one thing in this regard.
can we do it through some usb microcontroller with built-in A/D converter. can anyone tell me the feasibility of this option and some useful links.

 

[pisoiu]

20mhz digital oscilloscope project

i want to ask one thing in this regard.
can we do it through some usb microcontroller with built-in A/D converter. can anyone tell me the feasibility of this option and some useful links.

Of course you can, but usually the sample rate of the A/D converters included in microcontrollers is too low for that purpose. For example, if you want to view a periodical signal with the freq at 1MHz, you need to sample it with a freq of 2MHz (according to Niquist), but in practice, if you want to see something usefull, you need to sample it at min 5MHz. Microcontrollers are too slow for sampling AND storing the data at that speed.

/pisoiu

 

[dainis]

digital oscilloscopes with fpga

i want to ask one thing in this regard.
can we do it through some usb microcontroller with built-in A/D converter. can anyone tell me the feasibility of this option and some useful links.

Of course you can, but usually the sample rate of the A/D converters included in microcontrollers is too low for that purpose. For example, if you want to view a periodical signal with the freq at 1MHz, you need to sample it with a freq of 2MHz (according to Niquist), but in practice, if you want to see something usefull, you need to sample it at min 5MHz. Microcontrollers are too slow for sampling AND storing the data at that speed.

/pisoiu

For example look Ubicom IP2022 risc CPU (price 23 USD), that have up to 160 MHz clock (160 Mips), and have internal Ethernet interface (with internal PHY), also USB interface ... I thinking that is possible on IP2022 making very simple and low cost digital oscilloscope wth analog bandwith 20 MHz ?

 

[pisoiu]

8051 project on oscilloscope

For example look Ubicom IP2022 risc CPU (price 23 USD), that have up to 160 MHz clock (160 Mips), and have internal Ethernet interface (with internal PHY), also USB interface ... I thinking that is possible on IP2022 making very simple and low cost digital oscilloscope wth analog bandwith 20 MHz ?

By using an external generated clock, for processor as well as for an external high speed ADC (because of tight clock jitter requirements implied in such applications) it would be possible. Internal RAM should be fast enough and with enough capacity (4kb max.) for this application. Internal ADC is definetely inappropriate for this (IP2022 datasheet, pag. 72: max. internal ADC sample rate is 48khz). The storage algorythm is dictating the max sampling speed, because for storage, it is necessary to perform RAM write operations as well as internal pointers updates.

/pisoiu

 

[Roughy]

oscilloscope on computer project

I need an oscilloscope schematic to build for a school project. Can anyone help? Or else can anyone give me a good websight where I can find some information? Thanks!! :turn-l:


Use the excellent search function in Forum before posting
bitscope.com has some sch search forthat and oscillosocpe here and you find quite a lot of links.

Cl

 

[simce]

digital osclilloscope project

Read this topic from the begining, and read rules of this forum...

 

[Roughy]

50 oscillscope projects

Hi everyone,
I need an oscilloscope schematic diagram to build for my final year project. The oscilloscope schematic I need cannot involve a PC. Can anyone help

 

[monnoliv]

xc9572 project hardware

Hi everybody,

DSO: 7th revision
This is a small revision, the optoisolators are replaced by galvanic isolator IC (register to see the schematics):

**broken link removed**

Regards,

 

[DrShoe]

adc in oscilloscope

A) Maby it's an idee to include a frequency counter using a prescaler like the bitscope did: https://www.bitscope.com/design/hardware/?p=5

B) You should add a capacitor to the REF 4.096V

C) Some USB considerations:

There is a simple way to let windows detect a: USB 100MS Digital Scope
By changing FTD2XXX.inf and use a 'own VID & PID' with mprog.
vendor 0403 (dont change) product ID Exxx (change)

My company received 10 product ID's for free from FTDI, but if you use a random one there is only a chance of 1 in FFFF it's double.

See helpfile for Mprog (section D2XX Driver customizing) or PM me

 

[monnoliv]

c8051f320 altera jtag

A) Maby it's an idee to include a frequency counter using a prescaler like the bitscope did: h**p://www.bitscope.com/design/hardware/?p=5

It's a good idea but it's not as simple to do when using the same inputs as the ones for the scope since the prescaler (finite impedance) must not degrade the signal. With a separate input, it's more simpler (NB: I saw on the bitscope schematics that the prescaler input impedance is +-50 ohm).

B) You should add a capacitor to the REF 4.096V

Yes thks... and we've to choose between the two REF IC !

There is a simple way to let windows detect a: USB 100MS Digital Scope
By changing FTD2XXX.inf and use a 'own VID & PID' with mprog.
vendor 0403 (dont change) product ID Exxx (change)

My company received 10 product ID's for free from FTDI, but if you use a random one there is only a chance of 1 in FFFF it's double.

See helpfile for Mprog (section D2XX Driver customizing) or PM me

I've already did it in a previous project (see the other project on the site). I've putted my own PID and changed .inf file accordingly.

Regards,

 

[DrShoe]

fpga based oscilloscope with all information

Ram: If i take a close look at the tds210 the display has a resolution of 320*200 or maby 400*300 so there should be no need for a 10 bit a/d converter. If the X-axis is 300 pixels and leave some room for streching the axis, 4 times more we need 1200 Bytes. (hope the acex got it) For every timebase the a/d coverter should use another sampling frequency. Or is this completely wrong?
If every (of 10) divisions on the screen got 30 samples the fastes time base is 300nS

 

[Sanjuro]

oscilloscope fpga interface

monnoliv:

Where is clock generator (U1) on your "Logic unit" schematic?

If you don't have FPGA look at QuickLogic FPGA (QuickRAM series) **broken link removed**

 

[monnoliv]

eoscope project

Where is clock generator (U1) on your "Logic unit" schematic?

U2 is the 100MHz clock generator

If you don't have FPGA look at QuickLogic FPGA (QuickRAM series) h**p://www.quicklogic.com/home.asp?PageID=297&sMenuID=314

Using CPLD + SRAM is the cheapest solution (SRAM are very cheap), the counterpart is that it's a bit more complex (address bus) then CPLD + FIFO.

Ram: If i take a close look at the tds210 the display has a resolution of 320*200 or maby 400*300 so there should be no need for a 10 bit a/d converter. If the X-axis is 300 pixels and leave some room for streching the axis, 4 times more we need 1200 Bytes. (hope the acex got it) For every timebase the a/d coverter should use another sampling frequency. Or is this completely wrong?
If every (of 10) divisions on the screen got 30 samples the fastes time base is 300nS

We've already discussed about the sampling depth. Having 32k or 64k seems to be an acceptable value. Concerning 8 or 10 bit resolution, one can have the same ADC package with 10 bits resolution instead of 8 for a little extra cost, then we choose 10 bits.

 

[Sanjuro]

fpga design for digital oscilloscope

For every timebase the a/d coverter should use another sampling frequency. Or is this completely wrong?

YES and NO for low frequency signal

Egzample:
You observe 10kHz signal, and you those eg. 100us/div and fs~3MHz. You save memory and its ok. But if there is some high speed impuls (<330ns) you dont see it.

 

[beshan]

project on portable oscilloscope

Hey

I was wondering if I can help with writing the necessary code for the DSO project to work. Is this been done already ? or is this project still in the hardware design phase.

beshan

 

[nikifena]

oscillopscope project

Hi gyis, some french 30Mhz PC based oscilloscope
**broken link removed**
but I don't think that is something good, and have too many elements.

 

[karmicthreat]

dso input stage schematic

Has anyone tried making real sampling circuit? Something that uses a sampling bridge to take sub millisecond samples and spread them across multiple ADCs? You could make a traveling wave sampler to break the signals fundimental frequency down into lower frequencies. Plus you could sample at a much higher accuracy and precision.

 

[monnoliv]

oscilloscope ghz fpga

Hey

I was wondering if I can help with writing the necessary code for the DSO project to work. Is this been done already ? or is this project still in the hardware design phase.

beshan

The code isn't written yet. The project is still in the hardware phase.
Simce is updating the digital part (CPLD + SRAM), then he'll make a proto. In the mean time I (ve to) draw the PCB for the analog part (that's stable now). The problem is the time to do such things. Then if you want to participate in writting the software, you're welcome to our DSO Team discussion group. I planned to write the software with C++ Builder because there is a lot of software components that ease the development.

 

[simce]

pc oscilloscope +firewire

I planned to write the software with C++ Builder

Maybe usage of QT3 libraries should be considered for cross platform compatibility.

 

[Ace-X]

usbasp cyclone

I planned to write the software with C++ Builder

Maybe usage of QT3 libraries should be considered for cross platform compatibility.

I also think it could be good idea. There is one nice open-source project of QT-based GUI for DSO at http://www.mtoussaint.de/qtdso.html which can be used as a starting point.

Ace-X.