Coss related switching losses (Eoss)

[CataM]

Which can't be true since, as you just pointed out, Eoff can't be negative, but Eon can grow indefinitely.

Yes and it is correct. Here is where you are tripping off.
As you can see from the derivation in post #15, Esw off while Miller = Overlap between IL and rising voltage - Eoss.
At turn ON, Esw ON while Miller = Overlap between IL and falling voltage + Eoss.

Let us say that we have a Coss (or we have added a capacitor in parallel with Coss) such that Overlap between IL and rising voltage - Eoss =0. In other words, Eoff = 0 !
However, at turn ON, we still have Overlap between IL and falling voltage + Eoss ! I have never claimed that Eoss should be avoided at turn ON !
I am claiming that Eon+Eoff=(Overlap between IL and voltage + Eoss) + (Overlap between IL and voltage - Eoss) = Overlap between IL and voltage only.

Please notice that I am using IL (which is the drain current) and NOT the channel current. That is the reason Eoss is subtracted, because using IL only for switching loss is mistaken ! Similarly, for turn ON, using only IL is mistaken. Eoss must be added for turn ON.

Let us see how Eon can grow indefinitely, while Eoff is zero.
Let us say we have a Coss and we have added a cap "Cs" in parallel with Cds for both turn ON and turn OFF (i.e. not like the turn OFF snubber, but like it is in a Class E PA).
At turn OFF, since we have such a huge combination of capacitors in parallel, they stole all the current from the source (IL) such that ichannel=0, that is Etransistor=Eoff=0, but there is a lot of energy stored in the capacitors.
In other words, we make Esw off during Miller = Overlap between IL and rising voltage - Ecapacitors = 0 <=> Ecapacitors=Overlap between IL and rising voltage (notice that ichannel=0 but IL since is constant, is not, so there is overlap between voltage and current at the DRAIN node).
Please notice that the rising voltage time will increase as much as necessary in order to overcharge those capacitors but still the transistor has zero channel current i.e. all the current goes to the capacitors.
Eoff=0.

At turn ON, Eon=Overlap + Ecapacitors. If you have overcharged capacitors, your Eon will rise as much as overcharged your caps are.

 

[mtwieg]

Let us say that we have a Coss (or we have added a capacitor in parallel with Coss) such that Overlap between IL and rising voltage - Eoss =0. In other words, Eoff = 0 !

Okay.

I am claiming that Eon+Eoff=(Overlap between IL and voltage + Eoss) + (Overlap between IL and voltage - Eoss) = Overlap between IL and voltage only.

You just said that for turn off:

Overlap between IL and rising voltage - Eoss =0

Therefore your equation for total switching losses should be:

Eon+Eoff=(Overlap between IL and voltage + Eoss) + (0) =Overlap between IL and voltage + Eoss

I am running out of way to explain this... surely you've tried simulating this, right?

 

[CataM]

But my point is still that (Eon+Eoff) may depend on Coss, so Eoss can't be ignored entirely.

I see you are not entirely convinced, even with the derivation provided in post #15. We can check whether I am correct or mistaken using SPICE simulation and hand calculation (already provided along this thread) if using a MOSFET with linear parasitic capacitors (because the nonlinear capcitors makes it more of a hassle) and have access to the channel current.
This can be easy implemented in e.g. LTSpice.

I have used the exact parameters of the IPB65R420CFD LTSpice MOS model but left out the parasitic capacitors and added them manually using linear ones.

Simulate it and see that due to the Coss, the channel current increases and decreases during turn ON and turn OFF respectively by 1A.
dV_ds/dt=Ig/Cgd
ichannel=IL +/- Coss*dV_ds/dt=5 +/- (10pF+10nF)*1mA/10pF =5 +/- 1.001 Amps.

Compute switching loss of the channel using the method I have showed to convince yourself Eoss is exactly nulled out.

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I think you are misunderstanding me by thinking that I compute switching loss via overlap between channel current and drain voltage and to that add/subtract Eoss. NO! Overlap between load current and drain voltage.

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PS: In the LTSpice sim, only Cgs reflects the LTSpice model of the MOSFET, Cgd and Cds were added just to give a 1 A decrease/increase in the channel current due to their charge/discharge.

 

[mtwieg]

Rather than typing in a long formula by hand, I'd rather just alt-click the FET to generate a trace of its total power dissipation (V(Drain)*Id(M1)+V(Gate)*Ig(M1)). That's the true dissipation.

Your assumption holds up (total Eon+Eoff=9.1mJ) until Cds is increased to around 50nF. Above that point Eoff becomes near 0mJ while Eon increases linearly with Cds. At Cds=100nF, Eon+Eoff=13.7mJ, at 200nF it becomes 22.3mJ, etc...

 

[CataM]

(V(Drain)*Id(M1)+V(Gate)*Ig(M1)). That's the true dissipation.

Id(M1) in that simulation is the channel current. Can you certify that using Id(Drain) (add a series voltage source with 0 volts) gives you the exact same result without adding the Eoss loss ?

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From post #22:

Therefore your equation for total switching losses should be:

Yes, that is right. It is what I have said in post #21 at the bottom.

 

[mtwieg]

Id(M1) in that simulation is the channel current.

It's the total current into the FET model's drain terminal. Unfortunately LTspice's nmos device doesn't allow you to probe its internals, so you can't easily see the currents through junction capacitances. But in this case we're adding an external Cds which is much greater than the FET's Coss, so this becomes irrelevant.

Can you certify that using Id(Drain) (add a series voltage source with 0 volts) gives you the exact same result without adding the Eoss loss ?

The thing we're trying to calculate is the power dissipation in the FET. That is, by definition, the product of its terminal voltages and currents (since in this case its Coss is negligible). If another formula gives different results, then it's wrong.

Yes, that is right. It is what I have said in post #21 at the bottom.

Your post #21:

At turn ON, Eon=Overlap + Ecapacitors.

My post #22:

Eon+Eoff=Overlap between IL and voltage + Eoss

See the difference?

 

[CataM]

It's the total current into the FET model's drain terminal. Unfortunately LTspice's nmos device doesn't allow you to probe its internals, so you can't easily see the currents through junction capacitances. But in this case we're adding an external Cds which is much greater than the FET's Coss, so this becomes irrelevant.

Why would I bother myself in describing the IPB65R420CFD when it is already in the LTSpice standard library ? Go through the MOSFET list and see that LTSpice already has it in its standard library (it is close to the bottom of the list).

I described exactly the same MOSFET with exactly the same parameters (go check them) but as you can see I have stopped at Cgs=900p. That means, if you do not specify the Cjo cap and Cgd caps, by default (go check LTSpice manual) they are 0, in other words, we have a MOSFET with NO Cgd nor Cds caps.
So I have added them using linear capacitors, this way we have access to the channel current !
If you read again post #23, you will see that that is the purpose of the simulation, to have access to the channel current.

If another formula gives different results, then it's wrong.

In fact, if you use your formula by adding Eoss to the loss, your formula gives wrong estimation. Using either the MOSFET loss with the channel current or with the drain current, without adding any Eoss, you have exactly (this means, all decimals are the same) the same energy loss (Eon+Eoff).
Please insert a 0V voltage source in the node called "Drain" to see the drain current and hence you can compute the loss using either the drain current or the channel current, giving exactly the same results.

See the difference?

No. From the context of post #21, Ecapacitors includes Eoss and any additional loss due to any additional cap (if any) that returns the energy to the FET (not like the Turn OFF snubber).

 

[mtwieg]

Why would I bother myself in describing the IPB65R420CFD when it is already in the LTSpice standard library ?

I see that now, good trick.

In fact, if you use your formula by adding Eoss to the loss, your formula gives wrong estimation.

Correct, adding something to a correct result makes it wrong. Why would you do that? It was already a direct measurement of power dissipation, no need to add anything to it.

Adding a source in series with the drain does not change the result, of course.

Have you actually looked at the results of the simulation? What do you measure for Eon and Eoff as you change Cds?

No. From the context of post #21, Ecapacitors includes Eoss and any additional loss due to any additional cap (if any) that returns the energy to the FET (not like the Turn OFF snubber).

I was referring more to the left hand side of the equations...

 

[CataM]

Correct, adding something to a correct result makes it wrong. Why would you do that? It was already a direct measurement of power dissipation, no need to add anything to it.

Adding a source in series with the drain does not change the result, of course.

Have you actually looked at the results of the simulation? What do you measure for Eon and Eoff as you change Cds?

I was not referring to the post #24 formula, but to what you claim over and over again that Eoss plays part into the overall switching loss.

Of course the channel dissipation is the real dissipation and the reference we check against to, so using the power dissipation provided in post #24 is our reference for switching loss.
Do you agree that in a real world circuit, we need to compute losses using the overlap between drain current (NOT the channel current) and drain-source voltage ?

Here is where we do not agree, from the beginning of this thread.

My claim:

• Eon=Overlap between drain current and Vds|turn ON + Eoss
• Eoff=Overlap between drain current and Vds|turnOFF - Eoss
• Eswitching=Eon+Eoff=Overlap between drain current and Vds|turn ON + Overlap between drain current and Vds|turnOFF

Your claim and some major manufacturers claim:

• Eon=Overlap between drain current and Vds|turn ON + Eoss
• Eoff=Overlap between drain current and Vds|turnOFF
• Eswitching=Eon+Eoff=Overlap between drain current and Vds|turn ON + Eoss + Overlap between drain current and Vds|turnOFF

Do you see the difference ?
Please check which claim is the correct one, comparing them with the real power loss dissipation which is provided in post #24, that is, using the access to the channel current.

What I have said in post #27 is: Eswitching using my claim = post #24 switching loss.

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I was referring more to the left hand side of the equations...

Please read again your post #22 and see that you were referring to the special case when Eoff=0. When Eoff=0, Eon+Eoff=Eon so it is exactly the same as I said in post #21 because I also was referring to the case when Eoff=0.

 

[mtwieg]

Of course the channel dissipation is the real dissipation and the reference we check against to, so using the power dissipation provided in post #24 is our reference for switching loss.
Do you agree that in a real world circuit, we need to compute losses using the overlap between drain current (NOT the channel current) and drain-source voltage ?

Whether we do one or the other doesn't affect our overall measurement of switching loss for a full period. It just changes the relative values of our measured Eon and Eoff. I haven't argued otherwise from the start (but it's pretty much irrelevant, since only Eon+Eoff matters). My contention is that total switching losses can depend on Coss.

Your claim and some major manufacturers claim:

• Eon=Overlap between drain current and Vds|turn ON + Eoss
• Eoff=Overlap between drain current and Vds|turnOFF
• Eswitching=Eon+Eoff=Overlap between drain current and Vds|turn ON + Eoss + Overlap between drain current and Vds|turnOFF

Actually I don't really endorse any of these definitions, they're all just approximations to the true total switching loss, which should always be found by measurement (or simulation).

 

[CataM]

Whether we do one or the other doesn't affect our overall measurement of switching loss for a full period. It just changes the relative values of our measured Eon and Eoff.I haven't argued otherwise from the start (but it's pretty much irrelevant, since only Eon+Eoff matters)

We agree then. So basically you are saying Eoss is nulled in a full period, that is what is meant.

My contention is that total switching losses can depend on Coss.

Yes, for Eon when Eoff is zero. If you are not stating what I have said, then you have contradicted yourself. You said only Eon+Eoff matters, but inside those, Eoss is nulled out.

Actually I don't really endorse any of these definitions, they're all just approximations to the true total switching loss, which should always be found by measurement (or simulation).

In a real life circuit you do not have access to the channel current, so you need to use the drain current. Can you see that using the channel current in the simulation I showed is just a trick to get to know if we have to add the Eoss loss to the drain current overlap with Vds or not (in other words, the channel current losses is just the reference we must match) ?

The point of this thread is: Should we include Eoss or not ?

Let us say you have a real life circuit and you have the drain current waveform and drain-source voltage waveform. Can you share how would you compute switching losses ?
Here is what I would do: I would use the claim in post #29.

 

[Easy peasy]

The amount of energy taken up by Coss during turn off ( and given over to channel dissipation at turn on) is so low for a typical power converter that it can be ignored for all but low power applications, where the mosfets used have lower Coss anyway ...

 

[CataM]

The amount of energy taken up by Coss during turn off ( and given over to channel dissipation at turn on) is so low for a typical power converter that it can be ignored for all but low power applications, where the mosfets used have lower Coss anyway ...

Yes, but what if there is high freq involved, that energy might not be ignored. So it is important to know if Eoss is nulled out or not.

 

[kojum]

Yes, but what if there is high freq involved, that energy might not be ignored. So it is important to know if Eoss is nulled out or not.

Hi,
this is a really interesting topic. I've always had doubts until recently while testing a high frequency converter for generation of short (1 us) high voltage pulses. The converter switches at really low currents (1-2 A) and has some conduction losses for the duration of the high voltage pulses. What I observed while measuring the power consumption (coming from the input power supply) is that it had a clear linear dependency with frequency and a quadratic dependency with the input voltage and this has clearly to come from Poss ~ f*Vds^2. Since conduction and regular turn-on and turn-off losses are really small, most of the losses would come from the discharge of Coss.
The way I see it is that at turn-off the load current splits between channel of the MOSFET and Coss and the energy to charge Coss comes from the input, at turn-on then this energy is dissipated in the channel of the MOSFET. So at turn-off the losses are lower than what you would measure, because current through the channel is actually lower and at turn-on the losses are higher than what you would measure, because channel current is higher.
The additional energy dissipation you have at turn-on is accounted for at turn-off, so I agree that the TOTAL SWITCHING LOSSES are given by the Id*Vd curve over the whole switching cycle. However for the total power consumption of your converter you will need to add the additional Poss, which comes from the Eoss that has to be provided at each turn-off and then is dissipated in the channel of the MOSFET at turn-on.

 

[CataM]

The way I see it is that at turn-off the load current splits between channel of the MOSFET and Coss and the energy to charge Coss comes from the input,

I think is a good approximation to assume that during turn OFF, the load current is kept constant (that is the reason I have represented it with a constant current source "IL") (is it here where I am mistaken, the load current can't be approximated with DC current source during turn off ?). Of course, in a real circuit, that would be the current of an inductor (I am referring to the clamped inductive load switching, not resistive switching).

If the source during turn OFF supplies additional current to charge the Coss caps, then we have Source Current=Channel Current + Coss current <=> IL+ICoss=Channel Current + ICoss which is NOT possible under the assumption of the load current not varying (i.e. DC current source).

 

[asdf44]

Yes, but what if there is high freq involved, that energy might not be ignored. So it is important to know if Eoss is nulled out or not.

Yes in this thread here I brought up that exact topic. I built a 166khz 400V bridge with small SMT fets and with silicon devices the losses at zero load ate up most of my thermal budget. Switching to GAN fets drastically reduced these losses (Transforms devices were drop-in replacements).

https://www.edaboard.com/showthread.php?t=370433&goto=newpost

At the time I tried to reconcile those results with theory but failed. The GAN fet datasheet parameters were better, but seemingly not enough to account for what I saw.

Anyway I wanted to quickly mention that somewhat similar topic. I may post again here I have more time to study this thread in detail.

 

[CataM]

I know there is a lot of misunderstanding and controversy regarding the Coss (Eoss) related switching loss. In some app notes it is included, in others not, just overlap losses.
The overlap losses did not account for the full switching losses in your converter ? It was more than that?

I encourage you to read what I am claiming and tell me if I am mistaken because this is not philosophy, it is not a matter of opinion, but mathematical derivation and finally backing up the theory at least with simulation. If I am wrong, sooner or later the mistake must be figured out.

I have showed the derivation in post #15 and the simulation (post #23) which both agree. Where is the mistake ?
Is a mistake to represent an inductive load with a constant DC current source during a hard switching instant ?

 

[kojum]

I think is a good approximation to assume that during turn OFF, the load current is kept constant (that is the reason I have represented it with a constant current source "IL") (is it here where I am mistaken, the load current can't be approximated with DC current source during turn off ?). Of course, in a real circuit, that would be the current of an inductor (I am referring to the clamped inductive load switching, not resistive switching).

If the source during turn OFF supplies additional current to charge the Coss caps, then we have Source Current=Channel Current + Coss current <=> IL+ICoss=Channel Current + ICoss which is NOT possible under the assumption of the load current not varying (i.e. DC current source).

The load current is constant, you are correct. The thing is that the source is not supplying any additional current to charge Coss, some of the load current goes to Coss in order to charge it and the rest through the channel, hence the actual turn-off losses are reduced. That's why when you turn off at very low load currents (in relation to the rating of your semiconductor device) the switching speed is quite constant no matter how much gate current your gate drive circuit provides, since your load can not provide more than that low load current to charge Coss.
The term Eoss has to be included in the total losses of your converter whenever you have a hard turn-on, which causes a dissipation of the energy stored in Coss. If you use ZVS, then the energy stored in Coss is not dissipated anymore and actually given back to the source.

 

[FvM]

Yes in this thread here I brought up that exact topic. I built a 166khz 400V bridge with small SMT fets and with silicon devices the losses at zero load ate up most of my thermal budget. Switching to GAN fets drastically reduced these losses (Transforms devices were drop-in replacements).



At the time I tried to reconcile those results with theory but failed. The GAN fet datasheet parameters were better, but seemingly not enough to account for what I saw.

Anyway I wanted to quickly mention that somewhat similar topic. I may post again here I have more time to study this thread in detail.

If I understand right, the discussion in this thread was about the Coss related losses of a single MOSFET (e.g. with resistive or inductive load). Advancing to push-pull circuits, e.g. a half bridge changes the picture considerably. You should be aware that the majority of Coss related hard switching losses is generated by charging Coss of the bridge peer during turn on due to the non-linear capacitance characteristic. It's a popular source of underestimating switching losses. A derivation of total Coss related switching losses was given in the linked thread, thanks for reminding.

 

[CataM]

Advancing to push-pull circuits, e.g. a half bridge changes the picture considerably.

Agree it changes.

A derivation of total Coss related switching losses was given in the linked thread, thanks for reminding.

There is a mistake in your derivation, I think.
Referring to post #11, 1st code of this thread: https://www.edaboard.com/showthread.php?t=370433&p=1586243#post1586243
In the second integral, when you change the variable, you are forgetting negative sign: V2=Vdc-V => dV2= -dV (notice the negative sign).
After you recalculate, you get Esw= -2*Eoss + Vdc²*avg(Coss(V)) which actually shows that if capacitors were linear, their energy would have cancelled out.

When one capacitor is discharging, the same energy is being picked up by the other one, of course, if capacitors were linear.