Assuring stability with Voltage Mode TOPswitch Flybacks?

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Hi,
We are trying to use TOPswitch HX and JX flyback control chips , but with transformers with NP/NS's
which mean that our design is not supported by their PI Expert Suite software.
Please help us to use TOPswitch's in such use case?

As such, we need to be able to calculate the gain and phase margin of our TOPswitch designs. However, we cannot do
this since TOPswitch modulator gains are the secret IP of Power Integrations.
And since the PI Expert Suite software cannot be used with our transformer's, we cannot assure stability
of our designs. This is bad because voltage mode converters offer additional problems with stability and so
must be done with a feedback loop calculation.

The TOPswitch is a voltage mode controlled chip (certainly when on or near max power).

Transient response testing is not sufficient to prove good stability margins with
voltage mode converters like TOPswitch….as the following article by Dr Ray Ridley discusses...

Transient response & Loop gains of power supplies (Dr Ray Ridley)



..with a current mode SMPS, you can get better gain and phase margins by simply lowering the loop
bandwidth.....but this is not so for voltage mode converters. As the above discusses.

So we then need to calculate the gain and phase margins. -But this isn't possible with TOPswitch, since
the modulator gains inside the TOPswitch are kept secret.

So in summary, for a voltage mode converter, one must calculate out the gain and phase margins....ie, you have to make out
the Bode Plots.....you dont necessarily have to do this with current mode converters......Dr Mike Engelhardt emphasis this in 1:55 to 2:30
of his video as follows...

...But how do we calc the Bode plots for a TOPswitch when Power integrations keeps the internal modulator gain a secret?
The modulator gain is needed to be known to calc out the Bode plot.

In the following communication, Power Integrations applications engineers actually state that the
feedback loop parameters of the TOPswitch internals are the secret IP of Power
Integrations and so are not divulged to the public. Therefore, without the modulator gain of the TOPswitch
we are simply unable to do the feedback loop calculation for the TOPswitch..


Page 47 of "power supply design, volume 1:control" by Dr Ridley states that for a voltage mode flyback.."The crossover frequency should be at least twice the resonant frequency".......by "resonant frequency" , Dr Ridley means resonance of Cout and L(sec). [or rather "LE", the effective secondary inductance since its flyback and not full or half bridge).

Also, Basso states that Voltage Mode Flyback crossover should be three times less than the RHPZ frequency (our designs go into
CCM at low mains and so RHPZ becomes an issue)
….the above two facts mean that there is only a narrow band of possibilities for the crossover frequency of a voltage mode flyback like TOpswitch. A little variance in the tolerance of the opto, or whatever, and the whole thing could go unstable. Not only that,
but TOPswitch designs often use a NPN in the feedback loop. NPN's have very poor tolerance, and so the chances of running into
stability at some point with a TOPswitch design is quite high.

Page 25 of AN-47 shows the NPN being used in the topswitch feedback loop....

AN-47

Incidentally AN57 does not refer to TOPswitch HX or JX as the following tells....

Page 4 of AN57 by power integrations suggests that the LC resonant frequency of a TOPswitch flyback
should be greater than 500Hz...

AN57

This imposes a tight limit on the TOPswitch output capacitance, and throws into peril any output loading which may also feature an extra , large
electrolytic capacitor....instability may well then ensue.

Do you know what lies behind this recommendation of LC resonant frequency >500Hz?
Is it the fact that with TL431 based compensators that feature the "fast-lane/slow-lane" paths, the Type 3 compensator
is especially poor when LC resonance is >500Hz?

Here's a bit more on the TOPswitch Flyback output LC resonance frequency being >500Hz...

I mean, supposing your TOPswitch flyback suffers high variance in the opto CTR because you have five different parts as being "OK" in the BOM and need that flexibility to keep costs and lead times down....Or suppose the ESR (or the capacitance itself) of your output caps is highly variable.....or supposing some customers connect loads which comprise additional electro caps, thus dramatically increasing the output capacitance...etc etc.......current mode controllers can shrug this off and stay stable...a voltage mode converter may well go totally unstable under such changeable conditions.....

Like was sais, if the TOPswitch design is from the PIXIS design suite, or from the PI Expert software, then your good.....but if not......then surely one is in danger of instability?
 
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Honestly, I'm not particularly motivated to read a post that doesn't show at least a simple diagram visualizing the topology of interest.
 
I personally think that using empirical parameters to determine an approximate value, designing the initial circuit and making the initial prototype, and then adjusting the component parameters based on the test response of the prototype until the power supply can work normally, and then inferring its working principle in reverse, may be more helpful for you to quickly produce the required power supply.
 
ToP switch are current mode - they have internal peak current limiters too, as always a slower volt mode loop is nested outside the current loop for volt control.

Else they would be completely unstable for all the CCM flybacks ( RHP zero ) that people used to make with them - side note - they include a wee bit of slope comp in the mix too ( which is virtually identical to Vin feed forward ).

And finally - load stepping is fine - it is a broader test than loop measuring as it excites any non linearities, small steps about no load, 5% to 100% and back, 40% to 90% and so forth - if you can find no ringing and the over/under shoots are OK, and the time to settle is OK - the psu will be OK - you can of course insert the standard 20 ohm resistor and do a loop test - but to be any good you must do it at Vin max/min, and for a range of loads at each . . .

Your premises are often " interesting " ( except not ) - you should really read all the available information carefully before posting ( anything ).
 
Schematic of TOPswitch flyback
Honestly, I'm not particularly motivated to read a post that doesn't show at least a simple diagram visualizing the topology of interest.
Thanks, Pse see attached

TOPswitch is Voltage mode..
ToP switch are current mode
Thanks, if you look at AN57 from power integrations, the first paragraph says they are voltage mode...
AN57
_______
When at, or near max power, the TOPswitch is in voltage mode.

________
The 4th post of this...
...shows a Power Integrations Apps guy saying that TOPswitch is a voltage mode controller


The following discussion notes how the TOPswitch is voltage mode and Power integrations engineers are defending the TOPswitch's use of voltage mode control..

__________
Page 9 of the TOPswitch datasheet shows the control mode.
As can be seen, when at Max or near max power, the mode of control
is not current mode.
The feedback opto current flows into the CONTROL pin. The amount of excess current over and above the operating
current of TOPswitch gets used to derive the duty cycle. (in inverse proportion).
This "excess current" is like the "error voltage in a "normal" PWM controller.
The way this is converted into a duty cycle is just like a voltage mode controller does it...ie, with
a ramp generator into a comparator with one input being the error voltage.
At maximum power, the primary current signal is not used to derive the duty cycle and as such it is not
current mode control.
The datasheet explanation makes it clear that at or near max power the TOPswitch dynamics is that of voltage mode control.
There is a peak current limit, but this is not used as in current mode control.

TOPswitch datasheet

_____________
Load stepping
And finally - load stepping is fine
...Thanks, indeed so, for current mode its fine, but it can miss important information with voltage mode converters.....as the following from Dr Ray Ridley says...

Transient response and loop gains of power supplies (by Dr Ray Ridley)

__________________________________
TOPswitch in CCM
Else they would be completely unstable for all the CCM flybacks ( RHP zero ) that people used to make with them
..Thanks, good point, and in fact, if you analyse every single PI Expert TOpswitch design, they always make the transformer so that the TOPswitch flyback never goes into CCM...even at the lowest VAC input.
 

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Thanks and merry xmas!

The TOPswitch decides duty cycle by the amount of excess current into the C pin.
The TOPswitchHX has a KTOP figure of 0.2/mA......That is for every mA of excess current, the Duty reduces by 0.2 (starting from the max which is usually 0.78.

..This forms an entirely analogous situation to the case of "pure" voltage mode control, where the D is decided by the artifical ramp getting to the level of the error voltage.
As such, the dynamics of TOPswitch when at or near max power, is Voltage Mode Control.

Incidentally, below 55% of I(max), the TOPswitch holds the peak current at that level, and then adjusts the frequency to keep in regulation.......so this is where TOPswitch starts to get like current mode control.

But at or near max power, and the TOPswitch is voltage mode control.

Your premises are often " interesting " ( except not )
Thanks, i would agree its interesting if thats what you mean...practically every company any EE goes to these days, wants you to do an offline Flyback with TOPswitch (because it gives a small , cheap, low component count solution)...often their design does not conform, or fit into PI Expert suite, and so you have to try and do the voltage mode control calcs (when Power.com dont give you the controller gains).....the customers dont even know that they are exposing themselves to dreaded voltage mode dynamics.....i mean, your opto goes obselete or nil stocked and you need to replace it with another with a different CTR...and your voltage mode dynamics go pear shaped on you.

Not to mention they then connect it to a load with a huge electro cap up front, and again you voltage mode dynamics send you into instability...because you hadnt accounted for that much bigger C(out)

As Dr Mike Engelhardt says at 01:55 to 02:30 of the below video, if you do a voltage mode controlled converter, then you must make out the bode plots and calc out the gain and phase margin...

There are a lot of unscrupulous engineers out there right now who are gazumping more responsible engineers off the job by simply agreeing to do a TOPswitch design for a customer (a TOPswitch design for which no PI expert or PIXIS solution exists)....and just let the customer "go to the dogs" if the use case etc changes such that instability due to voltage mode dynamics shows up....of course, by the time the customer has "gone to the dogs", the unscrupulous engineer has been payed and has hopped it. (bodge it and scarper)
 
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Respectfully - your reading comprehension is poor, the cited paragraph does not say the part is voltage mode but rather how to complete the volt mode loop - any moderately educated engineer would realise that volt mode only will not work at all well with RHP zero - and it is fairly poor for DCM too. Current mode ( how ever far it is admitted or not ) is crucial to the stable operation. As is usual for any half way good converter the volt mode ( slower ) sets the demand for the current loop ( faster ) giving lovely stability overall.
 

That's also my reading of HX datasheet. But what's your design problem then? You have defined modulator gain, what's missing for determing stability?
 

any moderately educated engineer would realise that volt mode only will not work at all well with RHP zero
Thanks..Though surely one just arranges compensation such that crossover occurs at more then 3x less frequency than the RHPZ?

Respectfully - your reading comprehension is poor,
Thanks, though i believe we are speaking at crossed purposes...
The purpose of these thread is...
1...To re-establish that TOPswitch is voltage mode
2...To calc out the Bode Plots for a TOPswitch design for which no PI Expert suite solution exists.

(we need to do this since we are modifying a TOPswitch design for a Machine DC rail in London, we are modifying it for higher power)

1) above is i would say done and dusted, TOPswitch is deffo a Voltage Mode Controller (when at or near max power) Page 9 of its datasheet (TOPswitch-HX) confirms this.
Also, Dr Basso confirms it in his book, so too do Power Int Apps Engrs.

The following old thread sheds more good light here...

You have defined modulator gain, what's missing for determining stability?
Thanks, the modulator gain for TOPswitch-HX is 0.2/mA. (Duty cycle change per mA)
So we will use this in the AN57 equations to calculate loop Bodes for one of their demo designs and compare it and see if same or not.
As P455 of the attached shows, this means the Gain needed for their equns in AN57 is -163V/A
"K(TL431)" is 565 to 1000
 

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it seems a course in reading is recommended:



note how the peak current is set or rather modulated in the differing modes - interestingly all of this operation is omitted from the internal drawings supplied.

any one who has ever designed similar controllers from scratch knows the significant advantage of current mode over only volt feedback for a very wide range of users who cannot analyse a system accurately enough to make volt mode work properly every time, with current mode even the dolts will get something working when they close the volt loop into the system devised by PI, with the current in the control pin setting a power level, it is suitably filtered ( 7kHz ) and current mirrored to use internally as a peak current reference.

Imagine the average user trying to get the volt loop just right and relying only on a peak current limit inside the PI device - disaster - due to the double pole in the system, the RHP zero, the fact that the user can dump any amount of C on the output - only current mode turns the output into a current source - reducing the system order - allowing a much wider range of attempts at closing the volt loop.
 
Thanks, but your reference above quotes those bits of operation of TOPswitch when occur when its at significantly less than max power.
(ipk at less than or equal to 55% of the ipk limit)
When TOPswitch is at or near max power, its in Voltage Mode Control.

..As in page 9 of the TOPswitch datasheet... (under "Pulse Width Modulator")

Thanks yes, this is why all Power Integrations PI Expert designs with TOPswitch have the Flyback in DCM for the entire mains VAC range.
 
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Hi,

..Aagh, just found a Power Integrations Flyback thats in CCM for the entire mains range..

So yes, that a Voltage Mode Flyback, and in CCM for the entire 90-265VAC mains range when at nominal power output of 65W...

The 65W Flyback report named "DER243" by Power integrations details a flyback and gives Bode plots for it.
The attached excel doc calculates the same gain and phase margins and crossover frequency as shown in DER243.
However, this was by setting the Q factor to 0.15 as per Power Integrations recommendation on page
6 of their AN57 App Note.
This is unfortunate since for that 65W flyback, the Q factor (as per Basso equation) doesn't calculate out at anywhere near 0.15.

Do you know how Power Integrations may have come up with this Q factor figure of 0.15?

Also, the equations on page 14 of AN57 for Error Amplifier transfer function had to be quite heavily augmented
in order to come up with the bode plots as in DER243.
(for anyone interested , the augmentations are listed in the INTRO page of the excel document.)

AN57

DER243
 

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There's no helping those that refuse to see the obvious - or can't see it.

All early PI designs went into CCM

how unlikely is it that PI would drop out of pk current mode at near full power - very unlikely - the gain change and the double pole would quickly lead to oscillation for solely volt mode - pk curr mode is the underpinning of the success of these parts - they don't shout about it - 'cos it would confuse the average punter, ( like adding slope comp to the internal curr signal lowers the Q ),
they give just as much info as needed to close the voltage loop.
 
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Basso's book does a full analysis of TOPswitch.....in this chapter Basso clearly states that TOPswitch is voltage mode when at or near max power.
"designing control loops for linear and switching power supplies" by Dr Basso.
pages 455 to page 483

Also, page 9 of the TOPswitch-HX datasheet confirms that when at or near max power, its in Voltage Mode Control.

When the load gets much lighter, such that the peak current becomes 55% (or less) of the max threshold peak current, then it then changes from voltage mode control and fixes the peak current at 55% of the max and then reduces frequency as load gets lighter still.
 

you and M. Basso are free to believe what ever you like. That does not mean you are correct. A mistake copied is still a mistake.
--- Updated ---

and, respectfully - you still can't read, at higher power the following applies:



from your page 9, what is described is a round about way of describing peak current mode - which you are apparently unable to spot,

i.e. " a reduction of on time " - as the peak current ref falls.

the peak current is also a major feature of all other operating modes - but only revealed to those with a higher level of reading comprehension.
 
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Thanks but Power Integrations Apps Engineers also declare TOPswitch is in voltage mode when at or near max power.

"Traditional" voltage mode uses an error signal into a comparator along with a ramp from an artifical ramp generator.
Power Integrations Voltage Mode does essentially the same, though the error signal is the excess current into the CONTROL pin, and the
"Processor" in the TOPswitch is programmed to reduce Duty cycle as the I(control) current increases.
The peak current is not acted on like it must be in current mode. (when primary current is above 55% of imax)

But in TOPswitch, when the peak current gets down to 55% of the max, then it changes to variable frequency mode and the frequency reduces as i(control) increases...and the peak current is then held at 55% of imax..........

But when at or near max power, the TOPswitch is in voltage mode.

Flyback in Current mode must involve the actual primary current ramp itself being fed to the
PWM comparator along with the error voltage. This is definitely not what happens in TOPswitch when at or near max power.
It is this direct sensing and control of the primary current which results in cancellation of the double pole of the power stage.
But this is not what happens in TOPswitch when at or near max power.

from your page 9, what is described is a round about way of describing peak current mode
Thanks but Im afraid not. Your quote just describes how when above 55% of imax, the TOPswitch has a look up table
of Duty cycle vs control current. (ie control current is just the excess current into the TOPswitch control pin.)
The "round about" logic that you provide could be used to say that Voltage Mode Control was in fact Current Mode Control.
I mean, in voltage mode control, the peak current will tend to reduce as the duty cycle reduces, but that doesnt mean its current mode control.

the peak current is also a major feature of all other operating modes
Thanks, but this post is referring to "what at or near max power".
ie, when the peak current is above 55% of the i(max).
______

Their is in fact a SMPS design consultancy in UK where they left a customer
design project for a 25W offline flyback with a junior, thinking its just
going to be in DCM and current mode control....so a doddle for the junior.
Then they realised that TOPswitch is a voltage mode controller (when at
or near max power) so they quickly took the junior off the job.
Specially since the junior had done it so that the flyback would be in CCM
when at low mains.
Though if Power Integrations design software can be used, then its not such a problem,
because that will compensate it properly for voltage mode control. But often one selects
a transformer ratio that means their software cant be used. (because their software calls out
a different transformer ratio than what is wanted)
 
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Please advise what is "vpeak" in the Voltage Mode CCM power stage transfer function
attached equation 2A-18? (ie, what is Vpeak for the TOPswitch?)
The one attached is for Buckboost but as you know this gets adjusted to be useful for the
Flyback.

The "vpeak" is the peak voltage of the ramp signal that goes into the PWM comparator
in Traditional Voltage Mode Control. However, TOPswitch does not use "traditional"
voltage mode control, and so there is not a "vpeak" value apparent.
However, what would you take as "vpeak" for TOPswitch?

We cannot use equation 14 or 15 of Power integrations AN57 because they comprise the assumption that Q=0.15, and this has no
apparent basis.

I believe that equation 11 , page 11 (gain of the power stage) in AN57 can be substituted for Vin/[ ((1-D)^2) x Vpeak ] in equn 2A-18 (attached), would you agree?

AN57
 

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it seems a course in reading is recommended:
Respectfully, Topswitch's documentation seems to be opposed to the concept of reading comprehension.

At most, I think it's clear that "variable frequency pwm mode" corresponds to peak current mode control (though in an unconventional manner, where peak current is held constant while off-time is varied). As for "Full frequency PWM mode", "Low frequency PWM mode", I honestly can't tell whether it's voltage/current mode or something in between from those paragraphs.

Figure 9 in their datasheet also creates a great deal of confusion, as it implies that both duty cycle and peak drain current are directly functions of control current (and only control current). Obviously this cannot be true, of course, but it's not clear which, if either, curve is believable.
 
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Thanks, yes i also noticed that...my take on it was that it is "monitoring" peak current during full frequency PWM mode....as it has to know when it gets down to 55% of imax, because then the variable frequency mode kicks in....indeed, just as in "traditional" voltage mode control, the peak current will end up reducing as the Duty cycle reduces......but as is known that doesnt mean its Current Mode Control.

Though its Voltage Mode control when in "full frequency PWM mode". This is as explained above and indeed, the whole of chapter 8 of Basso's book (stated above) is on TOPswitch, and Basso makes multiple references to TOPswitch being in voltage mode. Power Integrations engineers also declare it as Voltage mode control.

Certainly, its not in Current Mode Control, but if it was, then they would have to give the Ohmic value of the sense resistor, because that is a feedback loop parameter in Current Mode Control....so if it were in current mode control, then nobody would have a chance of ever making out the Bode Plots for it.

I believe they did not opt for current mode control possibly because they want TOPswitchs to be useable by beginners etc.....and current mode control is more liable to "turn on spike" issues...so they opted for voltage mode control. Their 2 Transistor Forward chip is also in voltage mode control. PI also have software which is used to do all the compensation components, thus mitigating the more difficult voltage mode control compensation problem...the problem is that TOPswitch Flyback designs with certain transformer turns ratios dont get treated by their design software......hence this thread where we are trying to work out the Bode Plots "Manually".
Power Integrations latest chip is the Innoswitch of course, and it does all its feedback loop compensation internally. I suppose you can just use Innoswitch in a flyback instead of TOPswitch.....though you have to be wary of potentially overvoltaging one of the sec side pins which connects to the switching node of the sec coil. (150V max?). The thing is TOPswitch comes in the nice TO220 style package, whereas innoswitch doesnt. Innoswitch in fact only comes in a SMD package.
 
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