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analog design solution of pulse creator question

yefj

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Hello There is a greate circuit shown below.Is goal is to convert power supply non sinchronios +12V -12V into sinchronios pulse.
It consists of many components which i am having problem to see how they work together.
Why the comparators have capcitor on one leg while the othe leg has resistor?
Why there is a diode after the BJT in the end?
Is there way ou could reccomend me to separate this circuit into parts so i could see the logic ?
LTSPICE file is attached.

Thanks.
1728849140482.png
1728849095904.png
 

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  • pulse_stabilizer.zip
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I suppose this continues the discussion about proper turn-On sequence for your 2W amplifier IC? To put the explanation into words might be: several delay stages depend on successfully getting through each previous delay stage. The first delay is applied to the positive supply. When successfully detected, another delay begins while the negative supply becomes stable. When that is successful, another delay begins (C10 does the task at this point). Then both supplies are passed through to the rest of the circuit.

It's not obvious from looking at the schematic but it performs some back-and-forth notification between the positive and negative sides. It's not easy to see there's a teeter-totter effect at work causing the different delay functions. Adjustments are necessary to many components, before the output timing occurs as you desire.

I can believe this part of the project is important because the turn-On sequence should be accomplished before any signal (any voltage) arrives at the input. Practically all advice says the input(s) at any IC should not exceed 1/2 V beyond supply rails. This means you should not input a signal while the IC is Off. If I'd kept this in mind I believe it would have saved some of my destroyed IC's.
 
Hello, node "e" is rising from -12V after the pulses stabilize.
There are PMOS and NMOS which need to be open simultaniosly.
What is the logic in using NPN with a diode to open these mosfets?
Also why M1 has 100uF capacitor at the gate while M2 has only resistors?
Thanks.
1729024000934.png
 
The design is comprised of the functions:
- supply voltage comparators
- on delay
- level shift
- output stage
The present circuit has several issues, e.g. ripple susceptibility as discussed in a previous thread. Also both outputs are not switching simultaneously and equally fast due to asymmetrical design.

Don't know how important these features are for you. I would rather restart from the scratch than trying to improve this design.
 

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