analog design solution of pulse creator question

yefj said:

Hello Brad ,How do i make it monitor +12V -12V?
How do i connect the chip?
regarding the Vcc i'll try to search more.

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I'm afraid my knowledge is running thin into supposition. Although it has 8 pins and 141 transistors and could make your design work easier, I think Onsemi would have to give a day's class to instruct users how to apply their chip in a practical manner successfully.

Although a Vcc supply up to 40V appears in their writeup, everywhere else tells of the chip operating on voltages 5V down to 0V. Several graphs indicate this. The datasheet gives schematics about dual positive/negative supply detection. Nevertheless more is required to make it all work. This IC achieves only a portion of your startup sequence.

Don't I spot Schmitt icons inside the op amps near pins 2 & 3?
I'd try cascading Schmitt triggers in a linear fashion to go step-by-step to achieve your startup sequence.

Hello Brad, I have made already the startup sequence.I just need to make the +12V -12V power supply pulse into sharp +12V -12V.
I have implemented a basic shmidt trigger as shown below and LTSpice simulation.
Also i Have built a circuit which converts bad +12V -12V as shown below into sharp pulse +12V -12V also LTSPICE simulation is attached.
I want to do the same result using a shmidt trigger ,What strategy should I use?
Thanks.

Your schmitt trigger appears to work as it should. I put this together although it's not complete. Again it's a question how to make negative and positive supply rails negotiate with each other, and in what order, then to turn on both supply rails. Missing devices may or may not need to run on a negative supply rail.

BradtheRad said:

Your schmitt trigger appears to work as it should. I put this together although it's not complete. Again it's a question how to make negative and positive supply rails negotiate with each other, and in what order, then to turn on both supply rails. Missing devices may or may not need to run on a negative supply rail.

View attachment 194827

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1. review detailed specs, for good performance, fault detection and recovery.
2. Don't waste time on arranging parts with no specs to define what is acceptable or not and what is best.

Hello Brad, There is an implementation very close to what I think you advised.
As you can see in the photo ,PMOS drain is not creating a +12V pulse on the output.
The NMOS drain creates -12V very well.
What could cause such a behavior in the PMOS drain?
LTspice portable folder is attached in the link below.

Thanks.

YOu should know the source and load impedance of each as they are different between common emitter, common collector and common source, common gate. Review these parameters and make the necessary change.

Previously I got my schematic half-working with AND gate and NAND gate to fill in the gaps, however I decided I should post a vague schematic instead of a faulty schematic. There's a lot of back-and-forth of Yes-No decisions and an issue that occurs later on shutdown: Question: Can the same schematic perform a reverse order shutdown? And what to do if a fault happens? Do we want everything to shut down in an orderly manner?

I'm remembering several weeks ago an early discussion about the startup sequence:

Dana suggested programmable devices:
www.edaboard.com/threads/voltage-delay-mechanism-question.412199/post-1779685

The amplifier datasheet has 5 lines of decision-making and smart checking. I think this looks like one of those cases that programming can succeed where linear electronic logic becomes baffling. And 5 more lines dictate the shutdown sequence.