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USB Blaster download cable design

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air2008

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hi,

I want to make a usb blaster download cable for Altera FPGA. Could you please give me some suggestions or schematic? Thanks.




air2008
 

usb blaster schematic

Hello air2008,

The attached pdf is the schematic of the Nios II Evaluation Kit 1C12 from Altera. Page 11 shows the schematic of the USB Blaster. But the programming file for the used CPLD is not free! So I think you have to buy the cable from Altera.


Bye,
cube007
 
usb-blaster

hi,

Thanks for your help. Anyhow, I decide to design a usb blaster by myself.
I noted that the Altera usb blaster used usb+cpld to configure fpga. It is important that it adopts the JTAG model but not the PS model to configure FPGA. So, I have to make clear that how do write the cpld code to make the blaster works well with Quatus.
 
usbblaster

Hello air2008,

That’s a good project. I think there are some people in the forum which are interested in a self made USB Blaster. Let us know if you have some new information.

Good luck,
cube007
 

usb blaster clone

This is very interesting indeed. I have made a board very simmilar to this, but with a Xilinx XC9536/XC9572 instead.

I would love to make a use of this board as a USB downloader bor Altera and Xilinx. I have put it on the side due to my recent move and new job, but it would be interesting to see what you make out of your project.

And thanks for the schematic of the NIOS II, page 11 is almost a copy o what I have ony my board.

BR,
/Farhad
 

lattice usb download cable

farhada:

I have finished the board desing in Protel 99se. However, I am now puzzled with the HDL code design for the CPLD in the USB blaster. Could you please give me some suggestions?


air2008
air2008@gmail.com
 

diy usb blaster

Hi,
Actually that is where the challenge is. The HW part is the easiest part, to make the unit act like a USB blaster is the most difficult of them all.

Also, you need to read the content of the EPROM of the flash memory on the USB blaster, the one that is connected to the FTDI chip, put logic analyzer in between the USB chip and the CPLD and capture the communication for a while, do that a few times and you may find a pattern of commands/logic between the 2. That is the only way I can thing of making the USB blaster compatible deivce, uless you have a way to read back the content of the CPLD on the Altera board and cack it :)

If you don't have access to a logic analyezer, then it is a much much more difficult task. You maybe able to put a SW deugger to capture the data sent to the FTDI driver on the PC (I doubt Altera uses the stadard FTDI driver thought).

Just my 2c,
/Farhad
 

usb-blaster clone

After disasm usb blaster driver - file jtag_hw_usb-blaster.dll some infos are found:

ftdi direct driver ftd2xx.dll called.

Possible device ID's :
VID_09FB&PID_6001
VID_09FB&PID_6002
VID_09FB&PID_6003

Ftdi serial EEPROM (after config info) contain blaster revision number.
Driver checked this number when staring.

Only thys function from ftd2xx.dll are used- Ft_read, Ft_write, Ft_setusbparam.

Packet length is changed dinamically Ft_setusbparam then only
ft245B are used, 245А is not supported. Bit-bang not used.

Can anibody sniff usb traffic by Bushound or other utilities? It is possible to find version of ftd2xx.dll with debug printing included?
 

usb blaster epm3128 code

khach,

The Ftdi is just like the cypress usb develop board, where its EEPROM contains the revision number, although the former is more easy to use than the latter.

Added after 3 minutes:

Farhad,

Thanks for your suggestions. There is a logic analyzer in my lab and I will try to capture the communication between the usb and cpld.

You said you have made a usb blaster for xilinx. How did you design the hdl codes in cpld?

air
air2008@gmail.com
 

usb blaster driver download

air2008 said:
khach,
Farhad,

Thanks for your suggestions. There is a logic analyzer in my lab and I will try to capture the communication between the usb and cpld.

You said you have made a usb blaster for xilinx. How did you design the hdl codes in cpld?

air
air2008@gmail.com
Click to expand...
Actually, this one of the million half done projects that I have done. This one I want to come back to soon after I have my workshop set up again (I have moved 8 times in the past 3 years to/from 4 countries! :0 ) so this time I am not planning to move for a while and will be able to finish some of the projects.

I started working on the code, but I gave up after the first round of work. I mannaged to work with the FTDI driver and send/receive data to/from the CPLDs. The CPLD was programmed in VHDL (very simmple code, just a simple state machine to controll the Read/Write sequence and timing), all the boards/ewquipments is now on its way from Ireland to France and hopefully I will have them soon and will be able to "play" with them again. I will be more than happy to share the ideas/files with others here.

BR,
/Farhad
 

usb blaster circuit

For correct reengeneering VHDL code for any CPLD version (Xilinx or Altera) some
tests need.
Is one transaction wrom FTDI to CPLD (one #RD pulse) produse only one transition on TCK line? Or one pulse on TCK? Or many pulses ( data from usb are serialized in CPLD)?
Can anybody check by oscilloscope this?
How many 24MHz clock periods contain in one TCK pulse ( CPLD state mashine counter size)?
 

usb-blaster download cable

Hello,

I have known how to designing the CPLD based on PS mode. I write a programmer utility to download the *.rbf file to the FTDI usb chip and the CPLD send the RBF bitstream according to the PS mode.

However, it could't be transparently compatible with Altera's Quatus 2. How to design the CPLD in order to let the blastercompatible with Quatus without the need to write our own programmer utility?

air2008
air2008@gmail.com
 

terasic blaster usb drivers

Hi,
There are some minir issues here that you need to consider.
air2008 said:
Hello,
I have known how to designing the CPLD based on PS mode. I write a programmer utility to download the *.rbf file to the FTDI usb chip and the CPLD send the RBF bitstream according to the PS mode.
Click to expand...
First of all, RBF based on Altera's programming book (https://www.altera.com/literature/hb/cfg/cfg_cf52007.pdf) is just for Cyclone and other FPGA devices. For CPLDs, I don't think you can create an RBF file, but I maybe wrong.

However, it could't be transparently compatible with @ltera's Quatus 2. How to design the CPLD in order to let the blastercompatible with Quatus without the need to write our own programmer utility?

air2008
air2008@gmail.com
Click to expand...
Designing the code, if you know what you want to do is pretty straight forward. You either write it in a highlevel language like verilog or VHDL (in the case of Altera, you can write it in AHDL) or you make a schematic of the design using the internal logic blocks and then compile and create your POF or JED file.

Altera has a very good tutorial that comes with the free versoin of the Quartus that you can use to create your code.

For downloading, I would say it will be easier to use a ByteBlaster compatible device and don't worry much about being able to re-program the device via USB. Specially since this device will be the one used for those kind of tasks and don't need to be re-programmed that often.

BR,
/Farhad
 

usb blaster cpld

Hi,
I know this is an old one, but any new about your idea? Did you spend any more time on it?

BR,
/Farhad
 

usb blaster virtual com port

the key IS the Logic in EMP7064,who has * it?
It was said that somebody in China has done it well.
 

usb blaster download cable

There are a few issues to deal with the USB downloader for CPLDs and FPGAs. The main problem is to make it compatible with the design from Altera.

I would really like to know if anyone has done anything similar to it and want to work together to fix it.

Cheers,
/Farhad
 

usb blaster driver dll

I have take a picture of the board, through analyze, I think clone the CPLD maybe possible, but difficult to do. A logic analyzer is absolutely necessary. Try to replace the 24MHz crystal with a lower one, it may be helpful to capture and analyze the signals on it's i/o pins.
 

master blaster usb firmware

USB blaster board picture
 

make a usb_blaster

Hi Cluck,
Thanks for the picutre.

I have now both a FTDI and a rather large CPLD board, I may have some time to work on the design but it is difficult to make it compatible with the Altera device if I don't know the communication protocole.

Anyone want to share knowledge, send me PM and I give you my contact.

Best regards,
/Farhad
 

usb blaster driver

VID/PID
09FB/6001 - USB Blaster
09FB/6002 - Cubic Cyclonium
09FB/6003 - Altera NIOS II Eval Board

Protocol looks a little similar to Altera BitBlaster protocol, differences full 8 bits are used.

0000 0000 NOP? *64 used to ensure the bit output buffer is empty
0001 xxxx ?
0e1z 11sc Set outputs c=TCK, s=TMS
e TDO ECHO bit (0= no echo)
z Tristate ?

D0 - TCK
D1 - TMS
D4 - Tristate outputs?
D5 - LED

If D7 = "0", then D4 eq JTAG TDI

D2, D3 - NCE, NCS ???.
 
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