Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

ASIC Design Methodologies and Tools (Digital)

Post thread
ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions
B
  • Question
Question Regarding Using Older nxtgrd Files with StarRC
Replies
0
Views
503
BrownieHaHa
B
F
  • Locked
  • Solved
[SOLVED] Need help in importing .LEF file to IC Compiler
Replies
1
Views
614
fky
F
K
  • Question
VCS Mixed Simulation VCS VHDL Verilog Mixed language simulation with UVM
Replies
6
Views
730
Kashif Minhas
K
H
  • Question
Seeking Recommendation for a Complete Chip Design Project to Study and Reference
Replies
1
Views
425
danadakk
danadakk
E
  • Question
Why Do Negative Delays Occur in Timing Reports and What Do They Mean?
Replies
2
Views
726
ThisIsNotSam
T
L
  • Question
Question about creating a LIB timing files for a mixed-signal hard macro
Replies
7
Views
1K
Mehvish99
M
L
  • Question
Conformal LEC problem
Replies
1
Views
544
温柔阴影
温
G
  • Solved
Issue with Missing TT Model in Sky130 Library for Simulation
Replies
1
Views
505
ThisIsNotSam
T
S
  • Question
Tcd density drc violations
Replies
3
Views
580
ThisIsNotSam
T
rishabh_1999
  • Question
DFT DRC's D8 D10
Replies
2
Views
1K
rishabh_1999
rishabh_1999
L
  • Question
LEC conformal
Replies
2
Views
573
Learner12
L
E
  • Question
Why doesn't clock transition time affect my timing analysis (PrimeTime)?
Replies
8
Views
1K
Mehvish99
M
S
  • Question
Assura gives DRC error even for a single device
Replies
4
Views
541
Sameerpy
S
M
  • Question
What is the meaning of this block in Cadence Virtuoso? My first time designing a layout, and this pops up randomly. (DIFFCON)
Replies
1
Views
536
ThisIsNotSam
T
Mak444
  • Question
Memory Stitching during scan
Replies
1
Views
878
mds07
M
M
  • Question
finesim measurement with variable threshold
Replies
0
Views
454
mds07
M
S
  • Question
"Error: [UCLI-003] Unknown flag or misspelled flag"
Replies
2
Views
1K
v_shah
V
Y
  • Question
Gate level logic simulation
Replies
1
Views
652
ThisIsNotSam
T
K
  • Question
input
Replies
0
Views
415
kimilee
K
S
  • Question
I am getting FLT-003 error msg in Primetime
Replies
0
Views
757
skr96
S

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top