I'm writing a cpu with verilog and now i'm on the synthesis stage. Vivado detected a combinational timming loop but I can not find how this loop occurs or how to eliminate it.
The message vivado gave me is as follows.
`[DRC LUTLP-1] Combinatorial Loop Alert: 7 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is cpu0/_if/q_rd_ptr_reg[3]_29. Please evaluate your design. The cells in the loop are: cpu0/_if/i___18_i_4, cpu0/_slbuffer/i___18_i_5, cpu0/_slbuffer/i___18_i_11, cpu0/_rs/i___18_i_13, cpu0/_slbuffer/i___83_i_2, cpu0/_if/i___84_i_1, and cpu0/_rs/i___373_i_18.`
I can not match the cell name or the net with the wires and regs in my source code. I think there is no obvious timing loop like "assign a=a" in my source code. May anyone help me out? I would appreciate it very much.
The message vivado gave me is as follows.
`[DRC LUTLP-1] Combinatorial Loop Alert: 7 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is cpu0/_if/q_rd_ptr_reg[3]_29. Please evaluate your design. The cells in the loop are: cpu0/_if/i___18_i_4, cpu0/_slbuffer/i___18_i_5, cpu0/_slbuffer/i___18_i_11, cpu0/_rs/i___18_i_13, cpu0/_slbuffer/i___83_i_2, cpu0/_if/i___84_i_1, and cpu0/_rs/i___373_i_18.`
I can not match the cell name or the net with the wires and regs in my source code. I think there is no obvious timing loop like "assign a=a" in my source code. May anyone help me out? I would appreciate it very much.