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Yes. But, my bad, i badley explained myself. The tb saves output on a file. I need to reduce this output (the product 256*2880 = 737280 line of output). The simulation time is a consequence of this product. I don't know if i explained myself.
Hi everyone. I have a component wich is simulated for 200 ms where 200 ms is equal to 255*2880*271 (approximately).
- 271 is the clock period in ns.
- 255 is a clock divider (8 bit counter).
- 2880 is the number of counts that the simulation must do (12 bit counter).
I need a way to reduce the...
Semi-solved. First the code:
FSM
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use std.env.stop;
entity fsm_stimuli is
port(
-- FSM SIGNALS
signal FSMclk : in std_logic;
signal FSMtc_write : in...
Sure. I had truble whit my internet line.
(To compact i have attached the files).
i did some modification. Now the code doesn't crash but it still doesn't write.
P.S: text_write write first line on csv with signals names and tc_write write tests cases.
EDIT: i saw that the fsm has been written...
Sorry but i'm a little rusty with VHDL. I write a fsm with this logic:
if simRESET = '1', stay state 0 (st0) else next_state
if simRESET = '0' pass on st1
In st1 if test_done = false write first line text. If test_done = true pass on st2
in st2 if test_case = '1' write line of text TC else pass...
Hi everyone, first of all sorry for my bad english.
I have a problem with this code. It generates a csv file where writes stimuli for a TB (external).
It writes a first line of text with signals name, in the second line should write the first test case (text), after this writes signals and then...
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