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[SOLVED] Zero Crossing Detector Circuit Evaluation

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d123

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Hi,

Old circuit idea for ZCD, I wanted to see if it could actually be used in the real world (and how to go from sim-world AC generator version to a practical implementation). Would appreciate objective comments on circuit design mistakes, reasons why it couldn't work as desired, and/or things that would be glitchy. Thanks in advance if you have the patience and time.

Block diagram:

zcd circuit block diagram.jpg



Original idea which has a transient result that (hopefully) shows the purpose of the circuit:

ZCD RISING FALLING BLIP OUTPUT 358VAC PEAK IN.JPG



The version I think could work as a real circuit:

ZCD RISING FALLING BLIP OUTPUT 358VAC PEAK IN WITH TRANSFORMER V3.JPG


Reasons I can think of why it might not work as desired and/or can't/shouldn't be made:

1) I think I'm not allowed to plug a home-made transformer-based power supply into the AC mains unless it includes PFC, even for a circuit that would draw about 60mA.
2) Possibly, this circuit only works correctly (i.e. correctly meaning that the rising square wave pulse always occurs on positive-going and falling pulse always occurs on negative-going zero crossings) if the phase and neutral of the plug socket are known - if the wiring is reversed then the positive pulse would actually be the negative-going zero crossing and vice versa. Is that so?
3) I have read several things today that tell me that the secondary output of a transformer is either 180º out-of-phase with the primary AC sine wave, or that it is only a few degrees out of phase, or that it is never out-of-phase... Which of these is correct?
4) I see that chatter/false zero crossings is very possible from something I read. With regard to 'distorted AC mains', I have no idea how to implement comparator hysteresis for 0V references. Is that the same as for any other hysteresis? Is it really necessary? According to sbaa356, Zero-Crossing Detection with False Trigger Avoidance:


sbaa356 distorted mains false triggering image.JPG


Thanks.
 

Hi,

I agree it depends on requirements.
Now you have a zero cross circuit, both halfwaves combined. Low part count.

There is no filtering, there is no hysteresis it is not perfectly symmetric (causing DC).
It may work for a lot of applications.
But when you try to drive AC motors, transformers... then even a little DC could cause the core to saturate.

I´ve done huge (several megawatts) SCR driven current controllers. Here you need independent ZC signals for both polarities. We need to ensure very low DC and very reliable signals even in rather noisy environment. There were a lot of units in the building each controlling several 1000A through SCRs. High dV/dt and dI/dt.

I began with a simple approach like in post#18, but ended in a PLL solution....
You started with a rather advanced solution, but ended in a rather simple one.
Hardware design is so different...


Klaus
 
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    d123

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That is working as expected.
The reason for the strange output when C3 is 1uF is the output pulse is so wide it gets a double inversion in the XOR gate. More normal values would be maybe 1K and 10nF.
(...)
As the R3/C3 time constant increases, so does the width of the output pulse, when you made the time constant too long, instead of just pulsing at the square wave edges, it started setting and resetting as C3 could no longer discharge back through R3 and the transistor quickly enough.

Brian.
Hi Brian,

Super explanation, thanks.
--- Updated ---

Hi,

I agree it depends on requirements.
Now you have a zero cross circuit, both halfwaves combined. Low part count.

There is no filtering, there is no hysteresis it is not perfectly symmetric (causing DC).
It may work for a lot of applications.
But when you try to drive AC motors, transformers... then even a little DC could cause the core to saturate.

I´ve done huge (several megawatts) SCR driven current controllers. Here you need independent ZC signals for both polarities. We need to ensure very low DC and very reliable signals even in rather noisy environment. There were a lot of units in the building each controlling several 1000A through SCRs. High dV/dt and dI/dt.

I began with a simple approach like in post#18, but ended in a PLL solution....
You started with a rather advanced solution, but ended in a rather simple one.
Hardware design is so different...


Klaus

Hi Klaus,

That is a very interesting insight indeed. Thank you.
 

... adding to Klaus's comment about DC offset, there will be some offset created by the half wave rectifier, it will cause slightly higher losses on one half cycle due to uneven loading in the transformer. However, you can to a great extent cancel that by using a full wave rectifier. As the AC has to be monitored in reference to a ground, you can use a center tapped secondary and two rectifiers while still monitoring the AC from one side only.

For large industrial applications and particularly in noisy environments, I agree a PLL is a good option but it would be considerably more complicated. PLL is used to duplicate the AC waveform in frequency and phase but with a slow response to instantaneous changes so noise is ignored. The ZCD then uses the PLL output instead.

Brian.
 
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