Writing testbench in verilog or e language?

[wilfwolf]

I prefer the opinion of take_care00. To block level, verilog can do well, yet to system level of large scale, e is more powerful

 

[sarath51]

As Cadence has acquired Verisity and ther is a strong rumor that "e language" is being pushed as IEEE standard for verification , the prospets of e based verification seems to high.

 

[zhangpengyu]

You should use E,it's also fast for block-level verification.

 

[junchaoguo51888]

the verilog platform is common, but may be it is not the best for you design

 

[funzero]

E is good .
It is designed to be a verification language .
and have a good support from verisity.

 

[Arnold]

if you have an E expert in your team, you can choose E, otherwise, using others. E is too difficult to learn, especially there is no experienced engineer mentoring you.

 

[andrewcbl]

Should be 'e' language if you can only choose from 'e' and verilog. 'e' has a lot of good features hardly found in verilog.

 

[foster_cn]

definitely choose E, at least you have a chance to study new staff

 

[hys]

There are always multiple approaches to verify any design. This actually depends of what kind of design do u have and what level of verification is expected to be done.

1. Incase you have small design with and lot of control logic and less data path, I would suggest you to use some tools like Cadence IFV and PSL for assertions. Yes.. I am suggesting ABV (Assertion Based Verification) here...

2. It is also possible to use Specman based environment... which is also robust and solid. This you can use irrespective of whether ur design is control intensive of data path intensive.

3. In case you are just doing a sanity check.. of some basic functionality... then it is okay to go ahead building a verilog testbench...

There are many more things that can be done... u just have to look at what u need to do..

 

[rake]

If I can choose ,then Systemverilog,of course!
It is the latest trendy,every vendor can support it and it is free.don't waste so many time in choose language.just throw your engery in finding your bug.

 

[alpeshchokshi]

system verilog or vera is better option

 

[hys]

You could have read the earlier messages... u wud have got the answer...

Anyway.... repeating again, VERA is going to be phased out sooner or later....
System verilog is better than that...

You could even use specman - e which is equally powerful as a verification tool.

Regards,
Harish
https://hdlplanet.tripod.com/
https://groups.yahoo.com/group/hdlplanet

 

[darylz]

for complex system, sv is better...