newbie_hs
Full Member level 1
I am debugging a 6 layer board for RE issue and the stackup is (S G G P+G G S).This is a 6 layer board.
The microcontroller is present in TOP(L1) layer and decoupling capacitor is placed in bottom layer(L6).
I was told that "When you decouple through vias, you are always going to get the IO switching signals
producing voltages across the impedance of the vias and this noise is then on the whole plane"
May I know how this is happening?
For BGA's we used to keep decoupling capacitor in bottom layer only.
The microcontroller is present in TOP(L1) layer and decoupling capacitor is placed in bottom layer(L6).
I was told that "When you decouple through vias, you are always going to get the IO switching signals
producing voltages across the impedance of the vias and this noise is then on the whole plane"
May I know how this is happening?
For BGA's we used to keep decoupling capacitor in bottom layer only.