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the AC analysis will run only at one specific DC point, not sure which one it will pick in this case (I guess the first). Please try to run AC with vdd at one single value e.g. 2.7V
Hi allennlowaton,
may I ask you if you know what you are doing - and why?
There are several forum members who are trying to help you.
Why don't you follow their recommendations?
* You are doing an ac analysis by sweeping the power supply? What do you expect by doing this?
* For stability analyses you need the loop gain. Why don't you show us this gain? In one of your graphs there was only the voltage at one node (instead the ratio of two node voltages); the same for the phase response.
* The last graph shows a curve designated as "gain" - however the axis is named as a current: "result I(in)" . Confusing!
* Something is wrong since the gain curve does not cross the frequency axis.
* Therefore, you have been asked to simulate the bias point. No answer!
* It was recommended to start simulations at lower frequencies. No response.
__________________
It's really not easy to help you.
LvW
the AC analysis will run only at one specific DC point, not sure which one it will pick in this case (I guess the first). Please try to run AC with vdd at one single value e.g. 2.7V
Hi allennlowaton,
may I ask you if you know what you are doing - and why?
There are several forum members who are trying to help you.
Why don't you follow their recommendations?
* You are doing an ac analysis by sweeping the power supply? What do you expect by doing this?
* For stability analyses you need the loop gain. Why don't you show us this gain? In one of your graphs there was only the voltage at one node (instead the ratio of two node voltages); the same for the phase response.
* The last graph shows a curve designated as "gain" - however the axis is named as a current: "result I(in)" . Confusing!
* Something is wrong since the gain curve does not cross the frequency axis.
* Therefore, you have been asked to simulate the bias point. No answer!
* It was recommended to start simulations at lower frequencies. No response.
__________________
It's really not easy to help you.
LvW
Hello LvW..
I would like to apologize for the inconveniences I caused.
As much as possible I'm trying hard to keep track on the recommendations of the forum members.
I need more time to squeeze in all of them.
post #37 shows the loop gain, the graph y-axis says (lin) I am guessing for linear scale
i am also guessing that the simulator will pick the first value of the DC sweep to do the OP of the AC analysis but we'll see if that's the case in a coming post
allennlowaton is a student so we need to cut him some slack
it is quite an interesting problem for stability as there is both a positive and a negative feedback loop and even though the negative loop should be completely dominant (much higher output impedance on that side), the loop gain still manages to rise at high frequencies.
You are welcome to weigh in because as far I can see it is not simple to stabilize this with practical values of capacitance... I am probably missing something simple...
---------- Post added at 01:08 ---------- Previous post was at 01:04 ----------
Hello LvW * You are doing an ac analysis by sweeping the power supply? What do you expect by doing this?
I made a mistake on this but I already showed a simulation result using a fixed Vdd.
* For stability analyses you need the loop gain. Why don't you show us this gain? In one of your graphs there was only the voltage at one node (instead the ratio of two node voltages); the same for the phase response.
* The last graph shows a curve designated as "gain" - however the axis is named as a current: "result I(in)" . Confusing!
The "result (lin)" is the resulting axis when using the function f(x,y) feature of the Avanwaves. It's the only way I can display the vdb(n5x) - vdb(n5) and the same with the phase also.
*you have been asked to simulate the bias point. No answer!
---do you mean the DC(currents and voltage) graphs?
* It was recommended to start simulations at lower frequencies. No response.
---I don't know how to execute this one. Please teach me.
*you have been asked to simulate the bias point. No answer!
---do you mean the DC(currents and voltage) graphs?
* It was recommended to start simulations at lower frequencies. No response.
---I don't know how to execute this one. Please teach me.
Hi allennlowaton,
1.) In case the ac analysis does not show the expected results the first item to be checked is the bias point.
As you know, each active device (transistor, opamp) needs a suitable operating point that is determined by dc voltages/currents through the circuit. Otherwise its output cannot swing around this point if excited with an ac signal.
Perhaps you remember that in my first posting I have asked for the kind of opamp power supply.
Your answer was: Single supply.
Because, in this case, it is sometimes a bit tricky to bias the opamps I have recommended to you to check the opamp bias points. That means: Determine the dc opamp output voltages. Each simulator program calculates such a bias point before starting an ac analysis - and it should be able to display these voltages.
In your case (single supply) the opamp output dc voltages should be app. Vdd/2. I wonder if this is the case. Therefore, I have asked you to check these voltages.
2.) Your ac analysis starts at 100 Hz. I suppose, this was specified by you in an appropriate box. Or not? It should be possible without any problem to start at 1Hz or even below.
3.) Here is my recommendation for simulating the loop gain:
Do NOT use the method with a large L and a large C. Drop these parts and do nothing else that to place an ac source (1 volt) BETWEEN the nodes N5 and N5x, respectively. Then, the loop gain is Vdb(N5x)-VDB(N5) and the phase P(N5x)-P(N5).
This method is (a) more simple than the LC method and (b) more exact in the lower frequency range.
4.) Comment (for specialists): This method is the first part of the method as proposed by Middlebrook (the second part needs a current source). However, if applied at the opamp output this method is good enough because the loading error is sufficiently small.
_________
Good luck, regards
LvW
From now on I would suggest to use a fixed supply of 5 or 5.5 volts.
From your information above I conclude that the dc gain of OP-A is 1.7/0.6=2.8
Watch the dc output of OP-A when slightly changing the dc voltage (0.6 V) at the pos. input node.
Does the output vary accordingly? For example: For dc input= 0.7 V the output should be app 2 volts.
OK, it seems that the operating points are in the quasi-linear region of the opamps.
Another question - independent on foregoing stability discussions: What kind of basic malfunction did you observe?
That means - what was the reason for you to perform stability analyses?
Added somewhat later:
My question is because I don't know the present state of your circuit. And - more than that - why are you always ramping the supply voltage? Don`t you operate with a fixed supply?
Hello LvW..I just want to obtain an IBIAS which is constant as much as possible.
But simulations shows some oscillations.
The circuit should work on the 2.7~5.5V range (Li-ion battery).
Anyways, the graphs below shows the result of adding a 10pF in between N5 and N3(as dgnani suggested).
But I can't explain what happened..
Comparing the above results with the diagrams presented with posting #22 I see a big difference.
What has been changed ? The former transient simulations looked better, didn't they?
More stages will introduce more poles and it makes stability worse usually. Generally, every stage will contribute one pole.
For stability, the loop is compensated to a one pole system that will be stable. So first, it is better to reduce pole number.
Then generate zero to compensate high frequency zero and leave the lowest pole as the dominate pole.
More stages will introduce more poles and it makes stability worse usually. Generally, every stage will contribute one pole.
For stability, the loop is compensated to a one pole system that will be stable. So first, it is better to reduce pole number.
Then generate zero to compensate high frequency zero and leave the lowest pole as the dominate pole.
while reducing the number of poles and zeros is definitely the way to go, notice that here the biggest problem here is actually the presence of 2 complex conjugate zeros that create that 'notch' feature in the loop gain, even when we reduce the opamp to a single stage I am not sure that will go away.
I am not sure what creates them (it is basically a gyrated cap somewhere) but adjusting the relative bandwidth of the 3 amplifiers (OPb and the 2 common source amps in the feedback loops) might be key.
One way out of this is too add 2 poles on top of the zeros but it would be nice to understand if there is a more elegant (and practical) way to fix this
_________ CORRECTION
it's 2 zeros not necessarily complex and most likely related to the Cgd of the two PMOS's in the feedback loop
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