Why the output stage of a NMOS input two stage OPAmp is source follower?

[mpig09]

Hi SunnySkyguy:

Thanks for your information.

In the two stage design, I just understand the normal knowledge, so I post this topic and wish to more understand OPA design.

Very thanks everyone's reply.

I have more understood the two stage OPA performance.

mpig

 

[CloudHou]

Update ;-)

Using a free time I designed two complementary miller opamps and check their performance.
1. Specification for both opamps:
* technology 0.35um 3.3V vdd
* dc gain >70dB
* phase margin ~70 degrees
* current consumption ~1mA (without biasing)
* load capacitance 10pF
* non-inverting buffer configuration
* reference dc voltage equal to half of supply

For current sources I'm assuming overdrive voltage ~0.33V while input transistor should work in moderate inversion (Vod~10mV) and current ratio between output and input equal to 8.

The table below shows my results:

	NMOS input	PMOS input
dc gain (dB)	75	71
PM (degrees)	69	69.6
GBW (MHz)	78.5	74
Noise Vrms from 1mHz to 1THz (uV)	71.3	68.4
rise time (ns)	3	3.3
SR+ (V/us)	49.6	41.6
SR- (V/us)	44.4	46.8
current cons (mA)	1.014	1.026
Worst case PSRR+ (dB)	~6	~30
Worst case PSRR- (dB)	~36	~6
input offset (mV)	1.3	1.26

Some screenshots with simulation results and circuit diagrams:
1. NMOS input pair:
**broken link removed**
**broken link removed**
**broken link removed**
**broken link removed**
**broken link removed**
**broken link removed**

2. PMOS input pair:
**broken link removed**
**broken link removed**
**broken link removed**
**broken link removed**
**broken link removed**
**broken link removed**

In fact both op amps has the same performance but maybe for other specification I will obtain higher differences...

Hello sir,

I'm going to share some self experience about optimizing op amps.

- Lower flicker noise
- Improved matching
- Higher gm in output stage
- Superior slew rates
- Much better PSRR

generally these advantages of using PMOS as the first input stage for a two stage op amp are correct for most cases.

I check the schematics of your testing op amps, I guess the key reason why u get almost the same performance is the compensate capacitor.

for PMOS input stage, u can use smaller compensate capacitor than NMOS input stage to achieve the same specification.

from my own experience, for example at 1.8V power supply designing a 900MHz GBW, 65dB, 65PM, 1000 V/μs SR, 1V swing op amp.

since we have to optimize our design(lowest power dissipation), we spent time and tired both NMOS/PMOS input.

the result finally comes out.

while using PMOS input pair, at the same power dissipation and achieved all the spec., it come out much better SR since you can use much smaller compensate capacitor.

another experience, at 1.2V power supply designing a 500MHz GBW, 60dB, 65PM, 500 V/μs SR, 0.8V swing op amp.

while using PMOS input pair, it can achieve lower power dissipation comparing to that using NMOS input pair.

In my opinion, the most important benefit for PMOS input is "Higher gm in output stage"

since the position of poles are mainly related to gm1(first stage input) and gm5(second stage input), for stability, the non-dominated pole should be at high frequency(2~3 times).

so the arrangement for PMOS input(lower gm) at the first stage, NMOS(higher gm) input at the second stage is much reasonable.

that's why choosing PMOS input can maximize the Slew Rate as Martin said in his book.

but I do agree that most of case the reason people choose NMOS or PMOS is just because of the CMIR.