My real question is the output stage of a NMOS input two-stage OPAmp
has a PMOS active load.
The output of NMOS input two-stage OPAmp is VGSp + the output voltage of the first stage.
Does it will clamp the supply voltage?
==>My answer : it will not clamp the supply voltage.
This structure is based on the bias current to build.
If I have any mistake, please correct me directly.
mpig.
No, for the same bias condition and transistors area we can obtain better matching for NMOS input diff. pair and pmos load- Improved matching
Slew rate depends only to tail current and compensation capacitor values.- Superior slew rates
Only PSRR+ is better when the output is made on nmos, PSRR- is as bad as PSRR+ for pmos output.- Much better PSRR
No, for the same bias condition and transistors area we can obtain better matching for NMOS input diff. pair and pmos load
Slew rate depends only to tail current and compensation capacitor values.
Only PSRR+ is better when the output is made on nmos, PSRR- is as bad as PSRR+ for pmos output.
In two stage opamp PSRR depends to compensation technique.
You can check for example a Patrick Drennan paper about matching from SSC 2001 or check his Ph.D. Also Bastos, Steyart, Tuinhot etc (many guys from esat-micas in Leuven) reached similar conclusions.Dominik Przyborowski said:No, for the same bias condition and transistors area we can obtain better matching for NMOS input diff. pair and pmos load
... Can you supply some backup data / paper reference.
I have both edition of this book, in second one it's on the page 252 ;-)... See "Basic Opamp Design and Compensation" by Johns & Martin, pg. 231.Dominik Przyborowski said:Slew rate depends only to tail current and compensation capacitor values.
We could use a triple-well nfets for better isolation, but still the most important contribution to psrr is caused by compensation technique, because the C_c is the highest capacitor in two stage opamp (with capacitance almost two orders of magnitude higher than internal mosfets capacitances) and for higher frequencies (higher then dominant pole) becomes biasing output transistor as diode so psrr could fall to 0dB (or in worst case goes below) until frequency reach to zero in psrr bounded with input transkonductance and C_c.With an ndiff input, high frequency noise will couple from the supply through the Cgs of the driving PFET and thenDominik Przyborowski said:Only PSRR+ is better when the output is made on nmos, PSRR- is as bad as PSRR+ for pmos output.
In two stage opamp PSRR depends to compensation technique.
the compensation cap to the output.
With a pdiff input, high frequency noise will couple from the substrate through the Cgs of the driving NFET and then
the compensation cap to the output.
You will typically use a quite / isolated substrate for sensitive analog blocks such as opamps. Therefore, would you not agree that noise
from the supply is typically worse than from the substrate. I have not seen the opposite but that is not to say it cannot occur. Have
you experienced such issues?
NMOS input | PMOS input | |
dc gain (dB) | 75 | 71 |
PM (degrees) | 69 | 69.6 |
GBW (MHz) | 78.5 | 74 |
Noise Vrms from 1mHz to 1THz (uV) | 71.3 | 68.4 |
rise time (ns) | 3 | 3.3 |
SR+ (V/us) | 49.6 | 41.6 |
SR- (V/us) | 44.4 | 46.8 |
current cons (mA) | 1.014 | 1.026 |
Worst case PSRR+ (dB) | ~6 | ~30 |
Worst case PSRR- (dB) | ~36 | ~6 |
input offset (mV) | 1.3 | 1.26 |
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