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Which simulator is better VCS or NC-verilog?

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vcs vs nc-verilog

VCS NC-SIM comparason have been discuss many times before in news group . The conclusion is it depend on the test case , some report nc-sim superior than vcs , others report the opposite result . Even the winner/loser still be not in far away , so this is on-going game between the 2 major eda vendors.
 

vcs ncverilog

vcs take much more time to compile verilog, while nc-verilog take less time.
 

two state ncverilog

does LDV 4.0 include the simvision ? or simvision is a stand alone progz ?
 

2-state ncverilog

Yes, LDV include a simvision, the gui, but i never use the gui.
 

vcs nc verilog

i use VC$ and i feel it's better than LDV.
now VC$ 7 MX released , it can simulate both verilog and Vhdl.
 

ncverilog latest version

what's the reason you like vcs than ldv?


lovelyic said:
i use VC$ and i feel it's better than LDV.
now VC$ 7 MX released , it can simulate both verilog and Vhdl.
 

vcs ncsim

which one you first use may be the best one , i think they are all good! :)
 

vcs vs ncverilog commands

Verilog simulator:
$ynopsys > C@dence > Fintr0nics > Others
(53.4%) (31.9%) (8.0%) (6.7%)

VHDL simulator:
@ldec > Syn0psys > Others
(77.7%) (20.1%) (2.2%)

Mixed Verilog/VHDL
C@dence > M0deltech > Others
(52%) (47%) (1%)
---------------------------------------------------------------
ref:
h**p://www,deepchip,c0m/items/snug03-06.html
(SNUG 03 Item 6) [05/14/03]
Subject: Syn0psys VC$, C@dence NC-S!m, Mentor M0delsim, Scirocc0
 

ncverilog vs vcs

aramis said:
Excuse me,
except VCS, is there any simulator tool support vera-interface??

Vera use PLI interface to other simulates. :)
 

ncsim to vcs

Which one are you familiar with? For most of us, both /N/C/ and /V/C/S/ are powerful enough. They are almost the same level.
 

mixed verilog vhdl ncsim

VCS is compatible with Design Compiler!
 

vcs vs nc verilog

i love ncverilog
:D
 

differences between vcs and ncsim

i like vcs more than nc_verilog cause it compatible with Design Compiler!
 

vcs vs nc-verilog simulator

vcs is better since it runs faster than nc-verilog
 

vcs nc verilog 比較

VCS is faster than NC in my experience.

Added after 41 seconds:

VCS is faster than NC in my experience.

Added after 13 seconds:

VCS is faster than NC in my experience.

Added after 1 minutes:

VCS is faster than NC in my experience.
 

how to do tw state simulation using vcs simulator

It depends if you want more features or a faster HDL simulation engine. VCS is faster and I think more popular. NCVerilog is bigger.
 

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