which bandgap structure is better

[flushrat]

I run tran simulation of the two bandgap structures in attatched picture, A's output is 1.2V, but B's output is oscillating.
And I run ac simulation and found at DC frequency, both loops are positive feedback. The difference is that structure A's loop gain <1, while structure B's loop gain > 1.
Can anyone tell me should choose which one and the reason?
Or suggest me some material.

Thanks in advance.

 

[SkyHigh]

Choose the one with loop gain <1 because it is definitely stable.

 

[flushrat]

But structure B's phase matgin is more than 120
also stable.

 

[Y.C Park]

Hi

I think ~~
The only difference of above schematic is size of PNP transistor and resistor location.
For the layout convenience, Normally the PNP transistor size is 1:8.
So, which circuit is more prefer?

If I were you, I will choose A.
The reason why the bias current of constant-Gm bias circuit is determined
by ≈2/β*R² (if the MOS aspect ratio is same).
According to concept of BGR, above circuit make a PTAT current block.
I would like to send A circuit's PTAT current to temperature compensate block.
( PMOS current mirror location)

Any idea?

Thanks!!!

 

[lovseed]

Someone had seen this paper?

AN IMPROVED BANDGAP REFERENCE WITH HIGH POWER SUPPLY REJECTION


I have tried to use that circuit, but it oscillate in transient analysis.
And the feedback is also positive.

I think i have not grasp the spirit of bandgap design yet.

Can big bangs give some hint?

 

[laglead]

I think the purpose of cascode mirror is to attain good mirror property can be more immune to supply noise.
Q2 branch is the branch where PTAT current is generated.
Every MOS transistor has gate length modulation effect (or finite output resistance). So when VDD flutuates, P4's in picture B cannot track this flutuation and then current cannot be accurately mirrored to Q1 branch.

Two points should be satified:
1. Q2 branch current is mirrored to Q1 branch.
2. Q1's emitter voltage should be "mirrored" to R1's top side.

These two requirements are the conditions indispensible for the generation of PTAT current.

So, picture A is the choice.

 

[flushrat]

Thanks, I made a mistake in tran simulation. Actually the output of strucB oscillates.

 

[jerryzhao]

I think: design banggap must pay attention to the net between R1&N2, (name it net2), and the net between Q1&N1(name it net1).
Because we must let the Vbe1=Vbe2+Vr1.
So look from the net2 must nagative feedback.
Because the relation Vbe and Ic is ln.but the Vr1 and Ir1 is linear. the linear function is faster than ln function.
If the same niose to those two net ,the net2 must can came back, otherwise maye latched or oscillation.

 

[zkkbmy]

A is better than B for B is unstable! B is a positive feedback!

 

[davidwong]

I think: design banggap must pay attention to the net between R1&N2, (name it net2), and the net between Q1&N1(name it net1).
Because we must let the Vbe1=Vbe2+Vr1.
So look from the net2 must nagative feedback.
Because the relation Vbe and Ic is ln.but the Vr1 and Ir1 is linear. the linear function is faster than ln function.
If the same niose to those two net ,the net2 must can came back, otherwise maye latched or oscillation.

I still do not understand why look from the net2 must be negative feedback,
Can you explain it in detail?
thx

 

[jerryzhao]

in order to the voltage of net1=net2, we use the feedback. So the same current change at the net1 & net2, the voltage shift of net2 faster than net1. As the log function slow than linear if the same change.

 

[ipsc]

Let me try my hand at this.

Let me start with structureB. Suppose N4's (the one that is wideswing diode connected) gate voltage is 'V' (say this node is n1) and current though both legs is same and is equal to 'I' under stable conditions. Now suppose 'n1' voltage has become V+ΔV. Now the current in Q2(large area bjt) leg is increased to I+Δi2 and that in Q1 leg is increased to I+Δi1. The circuit will be stable in this state if Δi1=Δi2. It will return to it's original state if Δi1<Δi2. The circuit will be unstable if Δi1>Δi2. Here the point to be noted is when the two BJT legs move out of their stable point, for a given current rise Q2-leg (i.e. Q2+R1) needs more rise in voltage than Q1 leg. And also for a given decrease in current Q2 leg needs less decrease in voltage than Q1 leg. That means Δi2<Δi1 or Δi1>Δi2.

So structureB is unstable.

By using same logic it can also be proved that structureA is stable.

Point me if I am wrong.

'flushrat' I want to know how did you do AC analysis. Can you please post your AC analysis setup circuit?

Regards
--ipsc

 

[davidwong]

Let me try my hand at this.

Let me start with structureB. Suppose N4's (the one that is wideswing diode connected) gate voltage is 'V' (say this node is n1) and current though both legs is same and is equal to 'I' under stable conditions. Now suppose 'n1' voltage has become V+ΔV. Now the current in Q2(large area bjt) leg is increased to I+Δi2 and that in Q1 leg is increased to I+Δi1. The circuit will be stable in this state if Δi1=Δi2. It will return to it's original state if Δi1<Δi2. The circuit will be unstable if Δi1>Δi2. Here the point to be noted is when the two BJT legs move out of their stable point, for a given current rise Q2-leg (i.e. Q2+R1) needs more rise in voltage than Q1 leg. And also for a given decrease in current Q2 leg needs less decrease in voltage than Q1 leg. That means Δi2<Δi1 or Δi1>Δi2.

So structureB is unstable.

By using same logic it can also be proved that structureA is stable.

Point me if I am wrong.

'flushrat' I want to know how did you do AC analysis. Can you please post your AC analysis setup circuit?

Regards
--ipsc

Hi ipsc,
I still do not understand your explaination.
since current rise will not affect voltage voltage n1
why "for a given current rise Q2-leg (i.e. Q2+R1) needs more rise in voltage than Q1 leg. " ???

 

[szekit]

take away the pnp on both and u will get the beta multipllier reference. structure A is the right way to implment beta multiplier. B will oscillate.

 

[ipsc]

Hi ipsc,
I still do not understand your explaination.
since current rise will not affect voltage voltage n1
why "for a given current rise Q2-leg (i.e. Q2+R1) needs more rise in voltage than Q1 leg. " ???

But it do affect the source voltage of NMOS, hence the current in the transistor. To get a better picture let us take some fictitious numbers and analyze. Let the stable voltage of n1 (from now on let me call this node 'G' for brevity) be 2V and that of Q1 leg (node S1, source of N1) and Q2 leg (node S2, source of N2) be 0.7V.

Suppose V(G) become 2.2V. Now N1 and N2 try to push more current through Q1 and Q2 legs. But this increases the source voltages of them, which will in turn try to reduce the current. These two effects balance each other at certain source voltage. Suppose if the source voltage need's zero increase in voltage with increase in current, the source voltage will remain at it's previous value (This is the best case). In other words the increase in source voltage will be less for a case which needs less increase in voltage with increase in current. So the final values of V(S1) and V(S2) become say 0.72V and 0.76V. And we have, VG of N1 = VG of N2=2.2V. So Δi1>Δi2.

Hope I am able to make my point clear.

 

[zenisle]

consider the stable problem first.

 

[davidwong]

Hi ipsc,
I still do not understand your explaination.
since current rise will not affect voltage voltage n1
why "for a given current rise Q2-leg (i.e. Q2+R1) needs more rise in voltage than Q1 leg. " ???

But it do affect the source voltage of NMOS, hence the current in the transistor. To get a better picture let us take some fictitious numbers and analyze. Let the stable voltage of n1 (from now on let me call this node 'G' for brevity) be 2V and that of Q1 leg (node S1, source of N1) and Q2 leg (node S2, source of N2) be 0.7V.

Suppose V(G) become 2.2V. Now N1 and N2 try to push more current through Q1 and Q2 legs. But this increases the source voltages of them, which will in turn try to reduce the current. These two effects balance each other at certain source voltage. Suppose if the source voltage need's zero increase in voltage with increase in current, the source voltage will remain at it's previous value (This is the best case). In other words the increase in source voltage will be less for a case which needs less increase in voltage with increase in current. So the final values of V(S1) and V(S2) become say 0.72V and 0.76V. And we have, VG of N1 = VG of N2=2.2V. So Δi1>Δi2.

Hope I am able to make my point clear.

but it apply to both structure A and B ???

Can I understand in this way :

For structure B.
when the Q2 current increase, V(G) is increased.
then more current will flow though P2 and P4 due to the mirror current.
Thus it is unstable.

for structure A,
when Q2 current is increased, P2's gate is increased.
thus less current flow though P1, P3, N3, N1 and Q1.
as a result of mirror current, less current flow though Q2

 

[ipsc]

but it apply to both structure A and B ???

Can I understand in this way :

For structure B.
when the Q2 current increase, V(G) is increased.
then more current will flow though P2 and P4 due to the mirror current.
Thus it is unstable.

for structure A,
when Q2 current is increased, P2's gate is increased.
thus less current flow though P1, P3, N3, N1 and Q1.
as a result of mirror current, less current flow though Q2

It has to apply for both structures as our analysis is mostly independent of structure. The main point here is when the gate voltage of NMOS current mirror is increased, the current in the diode connected branch should be more than the other branch for the circuit to be stable because the NMOS diode connected and PMOS diode connected transistors are in opposite branches.

Regarding your way of understanding, it looks right, as that is what the final thing that comes out in my analysis.

Regards
--ipsc.

 

[Vamsi Mocherla]

Remember that there are two loops in the bandgap circuit.

Loop I
=====
Positive Feedback, which is the bootstrapped diode connected current mirrors which can potentially increase the current.

Loop II
======
Negative Feedback, which is the loop formed due to the diode in one branch and doide and resistor in another. The current through the resistor will determine the source voltage of the bottom NMOS transistors. Increase or decrease in the current will determine the increase or decrease in the source voltage of the NMOS FETs.

Implication
=======
Now for any stable circuit, the feedback is negative or the negative feedback should dominate the positive feedback. Hence both the feedbacks should act on the same node. Importantly the node at which they sum determine the stability of the circuit for them to be additive. The summing node in this case is the source node with transistors N2 and N4.

Hence the circuit on the left should be stable.

 

[davidwong]

Remember that there are two loops in the bandgap circuit.

Loop I
=====
Positive Feedback, which is the bootstrapped diode connected current mirrors which can potentially increase the current.

Loop II
======
Negative Feedback, which is the loop formed due to the diode in one branch and doide and resistor in another. The current through the resistor will determine the source voltage of the bottom NMOS transistors. Increase or decrease in the current will determine the increase or decrease in the source voltage of the NMOS FETs.

Implication
=======
Now for any stable circuit, the feedback is negative or the negative feedback should dominate the positive feedback. Hence both the feedbacks should act on the same node. Importantly the node at which they sum determine the stability of the circuit for them to be additive. The summing node in this case is the source node with transistors N2 and N4.

Hence the circuit on the left should be stable.

hi Vamsi Mocherla

for your explaination,
how can we see the negative feedback dominate the positive feedback?