Where to get schematics about SCRs full-wave triggering circuits ?

[Easy peasy]

A diac is in fact a triac, with internal resistors such that it breaks down to a volt or so ( as long as there is sufficient current to keep it on ) once the off state firing voltage is reached

 

[eagle1109]

Hi,


When the switch is open, then node may be seen as "floating". Floating means "undefined" .... anything can happen.
That's why I wrote "2) the switch is of no help. It makes things more difficult.".

An "open switch" is not the same as "Zero volts".

Klaus

Here's another simulation I did, and I think the diac here is continuously in conduction mode, the effect of oscillating as Brain told me that it should happen but it isn't so I think the simulation abilities here isn't perfect.

My understanding to what Brain told me, is that when the capacitor is charged up with the amount of voltage that should trigger the diac, it discharges and the diac conduct. As the capacitor is charging up again the diac should go back to off state. But that didn't happen, so anyway I don't know how to do it.

But I can change my experiment to use the UJT circuit or run the diac with an AC voltage source. What you think I should do ?


Here's the simulation.



The source voltage is 100V, R3 has a drop voltage of 38.9V the rest is 61.1V and R9 is also 38.9V. So should the voltage that conduct the diac ? so 61.1V - 38.1V = 22.2V. I don't know in the datasheet they mention that DB4 has breakover voltage from 35 - 45V.


Edit:
I increased the capacitor value so be able to observe the rise/fall of output voltage. If I return it to 100nF, the rise/fall would be so thin and zooming in the time on the scope actually diminish it and I can't go back.

 

[KlausST]

Hi,

My understanding to what Brain told me, is that when the capacitor is charged up with the amount of voltage that should trigger the diac, it discharges and the diac conduct. As the capacitor is charging up again the diac should go back to off state. But that didn't happen, so anyway I don't know how to do it.

Please tell which of Brian´s posts are you talking about. Can´t remember he talked about oscillation. But maybe...

Klaus

 

[betwixt]

With 100V and 10K in series it is possible the current through the Diac is sufficient that it doesn't turn off. That's why I wanted you to try 100K as well so you could see how it works. Instead you have added another 10K resistor where it would limit the discharge current from the capacitor and stop it oscillating.

Please go back to where I first described the Diac across the capacitor, with a 100K resistor and all you need to monitor is the voltage across the Diac/Capacitor with the oscilloscope. Set it to single shot with positive edge trigger, DC coupling and try a 1 second sweep time.

Brian.

 

[eagle1109]

OK, I only got one pulse, then it continues to have 22V output.



I just changed the capacitor value, to have more obvious charging time.

It charges until 42V ti drop to 22V contiuously.

- - - Updated - - -

Hi,


Please tell which of Brian´s posts are you talking about. Can´t remember he talked about oscillation. But maybe...

Klaus

In #74. He didn't say oscillating exactly

He said a sawtooth waveform .. and I also got the idea before that, that he wants to tell me about the simplest demo to observe the working principle of the diac.

 

[KlausST]

Hi,

Eventually we see the voltage at the capacitor rising until the diac triggers.
But - according datasheet - I can't see why it should stay at 22V. I don't even expect near 22V.

Out of curiosity I will add the DB4 to my shopping cart. It will take some (many? In times of corona) days...

In the meantime you may try another diac .... not from the same library.

Klaus

 

[eagle1109]

Yep, it should work in reality. But I believe the simulator didn't cover this effect.

I found it here:
https://www.bristolwatch.com/ele/diac.htm

It's the diac relaxation oscillator, there's also another one for the UJT.

So at this point, I think I should continue my work on triggering the SCR, and try to modify the AC circuit to get the proper diac triggering pulses.

I have now different versions of triggering in my mind:
1. Ordinary RC circuit
2. RC with DAIC
3. RC with UJT
4. Zero crossing detection connected to a UJT

These methods I guess are the most basic triggering circuits, so I should start here and until I develop a good experience about triggering systems.

Of course the world now has more advanced digital triggering systems for the sophisticated systems that have SCR or the other power devices.

 

[betwixt]

Racing Klaus.....

This is a DB3 Diac, 100K resistor and 100nF capacitor:


and this is what I see on the scope:


Brian.

 

[KlausST]

Hi,

I have now different versions of triggering in my mind:
1. Ordinary RC circuit
2. RC with DAIC
3. RC with UJT
4. Zero crossing detection connected to a UJT

Form the previous discussion you already should know that 1) not useful ... at least problematic
2) is good for analog phase angle control
4) is good for digital phase angle control

I recommend to go on with 2).
* fixed R, fixed C as timing control
* diac to get proper gate trigger
* measure the gate current with a scope

Don't longer use try and error method.
Calculate the values.
* R to get less than 250mW of power dissipation.
* C to get a useful phase angle

* measure the gate current with a scope
* then compare the scope results with the SCR datasheet limits and decide whether or not you need a current limiting gate resistor.

Show us what you do ... step by step.

Klaus

 

[eagle1109]

Hi,


Form the previous discussion you already should know that 1) not useful ... at least problematic
2) is good for analog phase angle control
4) is good for digital phase angle control

OK that's really good to know.

I recommend to go on with 2).
* fixed R, fixed C as timing control
* diac to get proper gate trigger
* measure the gate current with a scope

This is my next task to do.


But there's a problem in this regard which is that I can't control the amount of voltage that goes to the gate, thus I can't control the amount of current which should be constant during all phase control trigger process.

Don't longer use try and error method.

OK, I really have to get theoretical based calculations otherwise I won't get to the goal signal/current

Calculate the values.
* R to get less than 250mW of power dissipation.
* C to get a useful phase angle

* measure the gate current with a scope
* then compare the scope results with the SCR datasheet limits and decide whether or not you need a current limiting gate resistor.

Show us what you do ... step by step.

Yep I should do the rc tau calculation.


Just a quick experiment from the DB4 datasheet. I did their test circuit, they didn't put what voltages/currents I should get. But this is what I got on the simulation.



But also at the same time, I got a simulation warning as I just adjusted RV2 to 38% so 500k * 38% = 190k ohms.


Also why the signal on the capacitor and after the diac aren't in phase with source signal ? I really didn't the goal of this circuit.

But anyway I'm going back to the basic RC gate trigger. But I have to solve the phase/potential of the signal.

 

[betwixt]

I think we are going nowhere fast.
I can't confirm what your simulator tells you because I don't use Windows and as far as I know Proteus doesn't run in Linux. However, it seems to behave strangely and maybe the Diac model is incorrect. The picture in post #88 clearly shows what happens in real life and apart from using fixed components and a DC source, the schematic is essentially the same as in your last simulation. Where the sawtooth waveform suddenly drops is where the Diac conducts, if it had a 20 Ohm resistor in series with it like in your schematic, it would show the pulse as in the data sheet. I'll add a 20 Ohm resistor and show you the result tomorrow (it's too late at night here to start building things!).

Brian.

 

[eagle1109]

Racing Klaus.....

This is a DB3 Diac, 100K resistor and 100nF capacitor:
View attachment 158594

and this is what I see on the scope:
View attachment 158595

Brian.

The signal appears to be really stable. So this would a very/low cost oscillator for a lot of electronic systems. Where could this oscillator be used and how famous it's in current designs ?

- - - Updated - - -

I think we are going nowhere fast.
I can't confirm what your simulator tells you because I don't use Windows and as far as I know Proteus doesn't run in Linux. However, it seems to behave strangely and maybe the Diac model is incorrect. The picture in post #88 clearly shows what happens in real life and apart from using fixed components and a DC source,

Yep I'm not trusting the simulator like 100% it's at the end of the day a simulator that doesn't cover everything in life.

My goal from this thread is to develop good triggering circuit for half wave controlled rectifier and then try to develop another one for full wave.

I'm considering now to use a diac and a ujt for triggering.

the schematic is essentially the same as in your last simulation. Where the sawtooth waveform suddenly drops is where the Diac conducts, if it had a 20 Ohm resistor in series with it like in your schematic, it would show the pulse as in the data sheet. I'll add a 20 Ohm resistor and show you the result tomorrow (it's too late at night here to start building things!).

But they are using AC voltage and I was just testing their circuit. But it doesn't matter I'm trying to get back to my diac test circuit ..

 

[KlausST]

Hi,

But there's a problem in this regard which is that I can't control the amount of voltage that goes to the gate, thus I can't control the amount of current which should be constant during all phase control trigger process.

Quite confusing statement.
"I can't control the amount of voltage that goes to the gate" --> no comment
"thus I can't control the amount of current" --> why not?
"which should be constant during all phase control trigger process." --> constant? Why do you think it should be constant?

Also why the signal on the capacitor and after the diac aren't in phase with source signal ?

You use an RC circuit with AC source and wonder about phase shift ... really?
What do you expect from us?

Btw: where in the thread can we see that you are able to use Ohm's law?

Klaus

 

[eagle1109]

Hi,

I'm working on this simulation.

I just have a question about the best way to measure the gate voltage and thus calculating the gate current.



Is it enough to measure the rms voltage drop on R1 and then divide that by 0.7071 to get the peak voltage.

So to my calculations:

I(rms) = 0.34V / 10 ohms = 34mA

VR1(rms) = 0.34V >> VR1(p) = 0.34V / 0.7071 = 0.48V

Then, Ig = I(peak) = 0.48V / 10 ohm = 48mA


For ensuring calculations, I(peak) = I(rms) / 0.7071 = 34mA / 0.7071 = 48mA

But with the scope I'm getting that the voltage difference across R1 is 20V. So which is correct ?

Edit:
I forgot to mention the things I added to this circuit.
1. I added a diode to prevent negative voltages across C1 and also since I don't need the negative voltages to have negative triggering pulses which would needed in a TRIAC circuit.
2. I've put a series resistor 4.7k as I found it the most appropriate to get maximum current of 48mA at the gate which is the max rated current for this SCR.

- - - Updated - - -

I just thought of adding a voltage divider at the gate, is it a good idea ? I can split any incoming voltage the the balance I want.

According to the datasheet, if the gate voltage is at max which is 1.5V then the resistor that should be used in series with the gate is 33 ohms, so I tested that and I think I understood a little of how to get close to what the datasheet is telling me.

I used the voltage divider with the gate series resistor and got the required voltage/current values.

 

[KlausST]

Hi,

Issues:

I just have a question about the best way to measure the gate voltage and thus calculating the gate current.

* The gate voltage is meaningless (as mentioned in posts before, several times)
* you can't calculate the gate current from the gate voltage (at least not in a usual way). Gate_voltage is not proportional to gate_current, non ohmic behaviour, nonlinear
* your scope channel C needs to be inverted (also mentioned before) to get the gate current

Is it enough to measure the rms voltage drop on R1 and then divide that by 0.7071 to get the peak voltage.

No. This relationship (0.707) is only true for non distorted, sinusoidal waveforms without DC offset, which the gate current not is.
* The RMS current is not of interest when triggering an SCR, only the peak current. It can be measured with the resustor and differential scope mode, thus we recommended this method. There should be a peak. The peak triggers the SCR. Before the peak there should be almost zero current .... and is not much of interest. After the peak there may be any current (as long as it does not destroy the gate): zero, negative, positive, low current, high current ... it simply does not matter.

But with the scope I'm getting that the voltage difference across R1 is 20V. So which is correct ?

You measured the sum, not the difference. So your result is not correct.
But at least here you are close to a useful value: invert channel C.

1. I added a diode to prevent negative voltages across C1 and also since I don't need the negative voltages to have negative triggering pulses which would needed in a TRIAC circuit.

First we focus on "safe triggering an SCR" ... in future we will avoid malfunction. Then the diode may be of help. ...later

2. I've put a series resistor 4.7k as I found it the most appropriate to get maximum current of 48mA at the gate which is the max rated current for this SCR.

The maximum allowed gate current is far higher than 48mA.

I just thought of adding a voltage divider at the gate, is it a good idea ? I can split any incoming voltage the the balance I want.

No good idea. How often did we mention before that the gate voltage is not much of interest....I wonder why you still insist in talking about gate voltage....

According to the datasheet, if the gate voltage is at max which is 1.5V then the resistor that should be used in series with the gate is 33 ohms, so I tested that and I think I understood a little of how to get close to what the datasheet is telling me.

The 1.5V is not the allowed limit, the 48mA is not the allowed limit, thus the result is wrong. Not only the result is wrong, but also the way you used. With your way you calculate the internal resistance (although the gate has no resistive behaviour) ... but need the value of an external current limiting resistor.
I wonder where you have the "48mA" from. When I do a search at the datasheet PDF on "48" there are no hits.

and I think I understood a little of how to get close to what the datasheet is telling me.

I would be pleased if I could agree...

"48mA" maybe is the "max gate trigger current" ... not the "max gate current" ( which is 8A in my datasheet) .
The trigger current may vary from part to part (like the size of feet with humans) and it may vary with conditions like temperature.
Some may trigger with 30mA, many will trigger with 40mA, most will trigger at 45mA, but all of this type of SCR at all conditions will trigger with 48mA. Means your external trigger circuit needs to deliver at least (minimum!) 48mA of trigger current to safely trigger these SCR in all conditions.

Klaus

 

[betwixt]

Following on from post #91:

I actually used 22 Ohms in series with the Diac but that is irrelevant for this argument.
You will notice the same sawtooth waveform, it rises as the capacitor charges through the 100K resistor then the Diac triggers causing the capacitor to discharge through the diac and 22 Ohm resistor. The bottom trace is across the 22 Ohm resistor so it shows a voltage proportional to the Diac current. I am actually running it from 64V DC because thats the maximum my bench supply can manage but it works from anything from around 40V upwards.
Note carefully that the 100K resistor from a 64V supply cannot pass more than 0.64mA yet the current pulses are at least 7V high which across 22 Ohms means the current must be 318mA. What is happening is the capacitor is providing the diac current, not the 100K although a tiny amount does still come through the 100K as well.

A Diac is bi-directional and symetrical, if you use AC instead of DC it will still work but the pulses will be mirrored when the polarity is reversed. You would have to take into account the AC frequency and the RC time constant, obviously if the supplied voltage doesn't have time to charge the capacitor before it reverses and discharges it again, the Diac breakdown voltage may not be reached.

It is used commercially as a very low cost oscillator but the frequency depends on the applied voltage (hence capacitor charging time) and the tolerance and stability of components which for high voltages may not be too good. It is used for warning lamp flashers, audible alarms and the likes but is far too unstable for most uses.

Brian.

 

[eagle1109]

Following on from post #91:
View attachment 158619

I really appreciate your practical demonstration as I actually all my work is done with simulation

I actually used 22 Ohms in series with the Diac but that is irrelevant for this argument.
You will notice the same sawtooth waveform, it rises as the capacitor charges through the 100K resistor then the Diac triggers causing the capacitor to discharge through the diac and 22 Ohm resistor. The bottom trace is across the 22 Ohm resistor so it shows a voltage proportional to the Diac current. I am actually running it from 64V DC because thats the maximum my bench supply can manage but it works from anything from around 40V upwards.
Note carefully that the 100K resistor from a 64V supply cannot pass more than 0.64mA yet the current pulses are at least 7V high which across 22 Ohms means the current must be 318mA.

Is the circuit the same one as this ?

What is happening is the capacitor is providing the diac current, not the 100K although a tiny amount does still come through the 100K as well.

Yeah, the +ve pole of the capacitor is the one that holds the charge; for example, working with any electronic circuit that has a capacitor, and if the capacitor is charge then the only place to measure the voltage on that capacitor is the +ve pole. Which means it's the one that would discharge the current.

So in the circuit the capacitor charges up to the voltage level which is the required voltage to trigger the diac .. I really understand this point.

But that's the work of the electrolytic capacitor in this application. But what about non-polarized capacitors, do they work the same way of charging and discharging. I learned that non-polarized capacitors have difference uses, sometimes they are used for filtering purposes but I'm sure that it's a different story and it's a topic that I really want to study for a long time but I don't know when I should/must use a ceramic or polyester capacitor and at what value.

For the electrolytic capacitor, I know mostly it's used for smoothing an unregulated DC voltage and charging/discharging. These pretty much the most applications I know for electrolytic capacitor.


I know the capacitor is used for providing voltage stability at loads that I guess consume current more than voltage and causes the voltage and current to be not in phase; a famous example is the motors. But I don't which type is used in this application, is it specifically for the polarized capacitors or non-polarized capacitors or both types.

There are a lot of details I really want to learn.

A Diac is bi-directional and symetrical, if you use AC instead of DC it will still work but the pulses will be mirrored when the polarity is reversed.

OK yeah now I understand the shape of the output of the testing circuit I got from the DB4 datasheet.

You would have to take into account the AC frequency and the RC time constant, obviously if the supplied voltage doesn't have time to charge the capacitor before it reverses and discharges it again, the Diac breakdown voltage may not be reached.

So should I use the tau formula at this point to know when the diac should conduct ?

It is used commercially as a very low cost oscillator but the frequency depends on the applied voltage (hence capacitor charging time) and the tolerance and stability of components which for high voltages may not be too good. It is used for warning lamp flashers, audible alarms and the likes but is far too unstable for most uses.

Yep thanks for the info, it's a wide world in electronics industry and what directions that manufacturers use for any type of electrical/electronic device and the timeline of developments and advances is also a very important key to know about, what method is old but still works, if there a new method that works better ... etc.

- - - Updated - - -

Hi,

Issues:

* The gate voltage is meaningless (as mentioned in posts before, several times)
* you can't calculate the gate current from the gate voltage (at least not in a usual way). Gate_voltage is not proportional to gate_current, non ohmic behaviour, nonlinear
* your scope channel C needs to be inverted (also mentioned before) to get the gate current

No. This relationship (0.707) is only true for non distorted, sinusoidal waveforms without DC offset, which the gate current not is.
* The RMS current is not of interest when triggering an SCR, only the peak current. It can be measured with the resustor and differential scope mode, thus we recommended this method. There should be a peak. The peak triggers the SCR. . After the peak there may be any current (as long as it does not destroy the gate): zero, negative, positive, low current, high current ... it simply does not matter.

Yeah the peak current is what matters, I got that for sure from your previous answer and that's why I build my whole circuit to measure the peak current and not the rms current.

But how would I know that gate current ? I think the only way; at least for me because I have basic testing skills, so I think the best way is to put a resistor in series with the gate and measure with the scope the peak voltage and divide that voltage on the resistor, then I get the peak current.

Before the peak there should be almost zero current .... and is not much of interest

Yes, that's an important issue I was trying to solve until the last circuit, I think I minimized the problem better than before. I want it a short spike pulse which is all the wanted.

You measured the sum, not the difference. So your result is not correct.
But at least here you are close to a useful value: invert channel C.

Yep You're brilliant sir .. I just started to understand these points as I should have know before how to calculate the voltage differences.

Yep, C is where the lower voltage and D the higher, so to get the voltage difference I must get the difference VD - VC = VR1

Yep I got back and it's actually 4.5V ! and not 1.4V as I was hoping of

OK here things changed.

First we focus on "safe triggering an SCR" ... in future we will avoid malfunction.

I don't know how would I achieve that but I think the most important key for this aspect is to minimize the voltages at triggering circuit, which is to use resistors I guess. There would be power dissipation on these resistors and I remember that you mentioned that I shouldn't exceed 250mW for one of the resistors and that case if I use low power 1/4W resistors.

Then the diode may be of help. ...later

You mean I should remove the diode for now ? It it a known method for triggering a device that only needs the positive potential ?

The maximum allowed gate current is far higher than 48mA.

No good idea. How often did we mention before that the gate voltage is not much of interest....I wonder why you still insist in talking about gate voltage....

The 1.5V is not the allowed limit, the 48mA is not the allowed limit, thus the result is wrong. Not only the result is wrong, but also the way you used. With your way you calculate the internal resistance (although the gate has no resistive behaviour) ... but need the value of an external current limiting resistor.
I wonder where you have the "48mA" from. When I do a search at the datasheet PDF on "48" there are no hits.
I would be pleased if I could agree...

"48mA" maybe is the "max gate trigger current" ... not the "max gate current" ( which is 8A in my datasheet) .
The trigger current may vary from part to part (like the size of feet with humans) and it may vary with conditions like temperature.
Some may trigger with 30mA, many will trigger with 40mA, most will trigger at 45mA, but all of this type of SCR at all conditions will trigger with 48mA. Means your external trigger circuit needs to deliver at least (minimum!) 48mA of trigger current to safely trigger these SCR in all conditions.

The datasheet actually mention that the max peak trigger current is 8 A but that is not the wanted gate trigger current for the proper gate triggering.

The 8A is at specific period of time which is 20us if more it could destroy the SCR.



I numbered the points from the datasheet.

1. Here they mention that the max Ig is 50mA, when I was doing my calculations around 48mA I thought that 48mA is enough and not to hit the max rate.
2. I didn't understand what they mean by 160A !
3. This is the Peak gate current that is rated 8A but within specific time 20us.
4. Here they mention that the min gate current that would conduct the gate is 2.5mA and the max is 50mA.
5. Vgt, I think this is the required gate voltage, but I don't know what is the VD = 12V.

 

[BradtheRad]

is it specifically for the polarized capacitors or non-polarized capacitors or both types.

Non-polarized is preferable when true AC is present. However these tend to be bulky when you want more than a few uF.

An alternative is to connect two equal electrolytics back-to-back, thus making a non-polarized from two polarized type. Resulting Farad value is half of the value used.
It's a workaround rather than being ideal. Care should be given to make sure each capacitor stays healthy.

 

[betwixt]

A capacitor is a capacitor, electrolytic is just one type of construction. The charge is held across the capacitor, regardless of polarity so it isn't true to say it is only held at the positive end. Whether a capacitor is polarized or not depends on what type it is, generally only electrolytic types are polarized and they tend to be used when higher values are needed. There are 'non-polarized' electrolytics too but they are only used is special applications.

The issue of the time constant of the RC combination is simple, remember that the Diac only conducts when VBO is reached, if driven with AC the capacitor will alternately charge and then discharge then charge again with the opposite polarity, if the R or C value are too big, it will not have time to charge up to VBO and the diac will never have enough voltage across it to conduct.

You really need to study device ratings:
1. IGTmax is the MAXIMUM current you should ever need to trigger the least sensitive sample of that device, most will trigger at lower currents.
2. Most devices ratings are based on how long the specified parameter can be held before it overheats. You will see the different current ratings relate to different durations. The 160A reference relates to the voltage drop across it at that current and how much heat it would dissipate.
3. Yes, but that is the MAXIMUM rating that must not be exceeded, not the one you design to.
4. Yes, but measured under different conditions, the trigger current is somewhat dependent on the other factors.
5. Yes with 12V applied across the device and with a 33 Ohm load resistance.

Each user will design slightly differently and that device could be used for many purposes, the reason they give you such information in the data sheet is so you can see if it is suitable for the purpose you intended. It is a general purpose SCR which means it can be used in many applications, some DC, some AC and for completely different purposes. The manufacturer cant give all figures for all uses so they provide sample figures to demonstrate what it is capable of doing in different situations.

Brian.

 

[eagle1109]

A capacitor is a capacitor, electrolytic is just one type of construction. The charge is held across the capacitor, regardless of polarity so it isn't true to say it is only held at the positive end. Whether a capacitor is polarized or not depends on what type it is, generally only electrolytic types are polarized and they tend to be used when higher values are needed. There are 'non-polarized' electrolytics too but they are only used is special applications.

OK I understand now that the process of charging/discharging is the same but the difference is when using it with AC or DC.

One case of AC use is that it could charge/discharge from both sides. But other times it's used in DC circuits; like, in microcontroller circuits across the supply lines or the oscillator sides.

This one used across power lines:

Here with the oscillator:

Another example is the timer 555 circuit, that is connected on pin 5 and I remember that the use of a ceramic capacitor in that case is to provide more stability to the timing operation. But this link explains another function to that pin to connect a variable voltage to have more control on the duty cycle .. etc.

https://www.codrey.com/555-timer/pin5-and-555-an-abridgment/

Also pin 7:

Discharge: Pin 7 is called the discharge. This pin is used to discharge an external capacitor that works in conjunction with a resistor to control the timing interval. In most circuits, pin 7 is connected to the supply voltage through a resistor and to ground through a capacitor.

Also a capacitor can be used to discharge a voltage .. I'm not understanding this point completely but I have an idea.

=====================================================================

But anyway, an ordinary schematic for the 555 monostable has a 10nF ceramic capacitor on that pin, this link says connecting 10nF capacitor to eliminate any noise:

https://www.electronics-tutorials.ws/waveforms/555_timer.html

But how ? Is it the same function as smoothing the ripple voltage in power regulation circuits ?


The issue of the time constant of the RC combination is simple, remember that the Diac only conducts when VBO is reached, if driven with AC the capacitor will alternately charge and then discharge then charge again with the opposite polarity, if the R or C value are too big, it will not have time to charge up to VBO and the diac will never have enough voltage across it to conduct.

Yep pretty much .. I should adjust the RC tau to be within the period of +ve/-ve pulse at 60Hz which is 8.3ms. So any combination for my timing of the R & C values should eventually achieve the 8.3ms limits.

1. IGTmax is the MAXIMUM current you should ever need to trigger the least sensitive sample of that device, most will trigger at lower currents.
3. Yes, but that is the MAXIMUM rating that must not be exceeded, not the one you design to.

OK, so if I want to design a system that is using this specific SCR, that has max trigger current of 50mA and also could be triggered at 2.5mA. Then should I design the system to trigger the SCR from 50mA and above ?

Also what about the peak current that is 8A ? Should I for example trigger this SCR from 50mA to 8A ?

To me I guess I would trigger it at 50mA to minimize power consumption at the trigger circuit. Is this conclusion OK ?

2. Most devices ratings are based on how long the specified parameter can be held before it overheats. You will see the different current ratings relate to different durations. The 160A reference relates to the voltage drop across it at that current and how much heat it would dissipate.

Yeah but they are defining that the max continuous operation current is 80A. So how to consider the 160A ? They mentioned that 160A is when voltage drop is 1.55V across the SCR I think but for how long I can pass 160 across it ?

This is from the datasheet:

TM8050H-8D3 device is an
800V SCR thyristor suitable for applications where high power switching (IT(RMS) = 80
A) and low power dissipation (VTM = 1.55 V at 160 A) are key features.

4. Yes, but measured under different conditions, the trigger current is somewhat dependent on the other factors.

Hmm OK I don't know about the factors because I'm just working on a simulator. The industrial factors of course could be noise and heat, but I don't have other factors in my mind right now.

5. Yes with 12V applied across the device and with a 33 Ohm load resistance.

Oh yeah right !! wow what was I thinking ! I forgot to notice the RL that the L means the load

OK so those numbers means a simple test circuit that they recommend to test the operation of that SCR.

So if we use the same supply voltage to trigger the gate, then we need to get the Vg = 1.5V, so I have to design a simple voltage divider to put 1.5V at the gate and a series resistor 30 ohms then I get a gate current of 50mA.

The load current would be simply 12V/33ohms = 363mA

Each user will design slightly differently and that device could be used for many purposes, the reason they give you such information in the data sheet is so you can see if it is suitable for the purpose you intended. It is a general purpose SCR which means it can be used in many applications, some DC, some AC and for completely different purposes. The manufacturer cant give all figures for all uses so they provide sample figures to demonstrate what it is capable of doing in different situations.

Yep .. absolutely ! Thanks for the information

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I was working to learn the best current to trigger the SCR, as Mr KlausST told me it's really current driven device.

So I noticed in this simulation that the lamp isn't stable in active status it has some flickering so I observed the scope more and found these results:



The scope above has 3 marked gate voltages in RED.

3.09V, 2.59V and 1.34V.

So 3.09V and 2.59V triggered the SCR.

Is case where 1.34V at the gate the current would be 40mA which apparently doesn't trigger the SCR. So I guess I have to pass more current and ensure to deliver at least 50mA or more for reliable operation. Is this conclusion correct ?