architecture Behavioral of BS_SM is
-------BRAM-------
component BRAM_1 is
Port ( clk,we,en: in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (11 downto 0);
din : in STD_LOGIC_VECTOR (31 downto 0);
dout : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal en: std_logic;
signal Ram_Out,data_comp :STD_LOGIC_VECTOR (31 downto 0);
signal M_addr:STD_LOGIC_VECTOR (11 downto 0);
------------------
------States------------
TYPE State_type IS (Start,Compare_LR,Not_Found,Wait_memory,Read_Memory,M_calc,Compare, Found);
SIGNAL State : State_Type;
signal M: INTEGEr;
signal L: INTEGER RANGE 0 TO 3871 :=0;
signal R: INTEGER RANGE 0 TO 3871 :=3871;
begin
BRAM: BRAM_1 port map (clk,en,'0',M_addr,Target,Ram_out);
process (clk,rst,State)
begin
if (rst='1') then
State <= Start;
elsif (clk'event and clk ='1') then
case State is
when Start =>
L<=0;
R<= 3871;
State <= Compare_LR;
when Compare_LR =>
if (L<= R) then
State <= M_calc;
else
State <= Not_Found;
end If;
When Not_Found =>
Location <=-1;
Match <= '0';
Report "No Matching Found" ;
State <= Start;
When M_calc =>
M<= integer (L + R)/2;
State <= Read_memory;
when Read_Memory =>
M_addr <=std_logic_vector(to_unsigned(M,12));
en <= '1';
state <= Wait_Memory;
when Wait_memory =>
data_comp <= Ram_out;
State <= Compare;
When Compare =>
if(data_comp < Target) then
R<=R;
L<= M+1;
State <= Compare_LR;
elsif (data_comp > Target) then
L<=L;
R<= M-1;
State <= Compare_LR;
else
State <= Found;
end if;
when Found =>
Match <= '1';
Location <=M;
Report "Matching Found";
State <= Start;
end case;
end if;
end process;
end Behavioral;