What the best way to store data of size ( 90,000 * 32) bit (taken from a text file) using VHDL?

[MSAKARIM]

Your not_found state has no exit

Your not_found state has no exit

The used target value is inside the RAM, so it shouldn't go to "Not_Found" State. so, why it goes to this state?

--- Updated Jan 25, 2021 ---

Too coarse time scale. I guess there are multiple state transitions not visible in the wave. Zoom in to the first clocks after reset deassertion.

Here, the used Target value is the first element in the ram and it gives me a wrong location (First calculation of M and stops at it, it should repeat until it reaches the exact location), also I observe some unsynchronization
I can't catch where is the error exactly inside the code.

 

[ads-ee]

Not that this has anything to do with the problem, but you have an uninitialized RAM we.
In the real world this could potentially cause problems. You should initialize all control signals at reset.

Here, the used Target value is the first element in the ram and it gives me a wrong location (First calculation of M and stops at it, it should repeat until it reaches the exact location), also I observe some unsynchronization
I can't catch where is the error exactly inside the code.

Based on the waveforms you are not accounting for the delay to read the RAM. You should be updating ram_out after you've done the compare.

Maybe you should draw a FSM bubble diagram to clarify what you need to do and when.

 

[FvM]

Using Ram_out instead of data_comp in compare state should fix the timing problem.

 

[ads-ee]

Using Ram_out instead of data_comp in compare state should fix the timing problem.

Well not according to the code snippet below. The comparison is done in the Compare state and the values from the waveforms in post #41 show that data_comp and Target are identical when in the Compare state.

---

Code VHDL - [expand]
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When Compare =>
if(data_comp < Target) then      -- this checks for data_comp < Target
R<=R;
L<= M+1;
State <= Start;                  -- then go to Start state
 
elsif (data_comp > Target) then  -- now check for data_comp > Target
L<=L;
R<= M-1;
State <= Start;                  -- then go to Start state
else                             -- the default of data_comp = Target
Location <=M;                    -- Gee, you don't specify the state to go to....of course you never leave the Compare state
end if;

---

The problem stems from the issues with how the FSM doesn't specify the state transitions in various branches.

Like I posted before draw an FSM diagram to determine what should happen for every condition and then don't just leave out state transitions like you do here.[/syntax]

 

[MSAKARIM]

I really appreciate all help, this discussion helps me.
I will post in this comment the recent updates of my code

Here the semi-code of the algorithm what I want

Here, The FSM that I want to execute:

My Recent VHDL Code, " Note I used (en) for the RAM"

architecture Behavioral of BS_SM is
-------BRAM-------
component BRAM_1 is
Port ( clk,we,en: in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (11 downto 0);
din : in STD_LOGIC_VECTOR (31 downto 0);
dout : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal en: std_logic;
signal Ram_Out,data_comp :STD_LOGIC_VECTOR (31 downto 0);
signal M_addr:STD_LOGIC_VECTOR (11 downto 0);
------------------
------States------------
TYPE State_type IS (Start,Compare_LR,Not_Found,Wait_memory,Read_Memory,M_calc,Compare, Found);
SIGNAL State : State_Type;
signal M: INTEGEr;
signal L: INTEGER RANGE 0 TO 3871 :=0;
signal R: INTEGER RANGE 0 TO 3871 :=3871;
            
begin

BRAM: BRAM_1 port map (clk,en,'0',M_addr,Target,Ram_out);

process (clk,rst,State)

begin
if (rst='1') then

State <= Start;

elsif (clk'event and clk ='1') then

case State is

when Start =>
L<=0;
R<= 3871;
State <= Compare_LR;

when Compare_LR =>
if (L<= R) then
State <= M_calc;
else
State <= Not_Found;
end If;

When Not_Found =>
 
Location <=-1;
Match <= '0';
Report "No Matching Found" ;
State <= Start;

When M_calc =>
M<= integer (L + R)/2;
State <= Read_memory;

when Read_Memory =>
   M_addr <=std_logic_vector(to_unsigned(M,12));
   en <= '1';
   state <= Wait_Memory;
    
when Wait_memory =>
   data_comp <= Ram_out;
   State <= Compare;

When Compare =>
if(data_comp < Target) then
 R<=R;
 L<= M+1;
 State <= Compare_LR;
 
 elsif (data_comp > Target) then
 L<=L;
 R<= M-1;
 State <= Compare_LR;
 else
 State <= Found;
 end if;
 
when Found =>

 Match <= '1';
 Location <=M;
 Report "Matching Found";
 State <= Start;
end case;
end if;
end process;

end Behavioral;

 

[ads-ee]

You need to put all the signals assigned in the FSM into the reset branch of the if, otherwise you will get synthesis warnings and possible synthesis and simulation mismatches.

 

[MSAKARIM]

You need to put all the signals assigned in the FSM into the reset branch of the if, otherwise you will get synthesis warnings and possible synthesis and simulation mismatches.

Now I have a problem that RAM_out is not initialized, although I tested the RAM alone it works will

and I put all signals in Rest branch like:

if (rst='1') then
L<=0;
R<= 3871;
Location <=-1;
Match <= '0';
en <= '0';
M_addr <= (others => '0');
M<= 0;
data_comp <= (others => '0');
State <= Start;

 

[ads-ee]

I don't think you have ever posted your RAM code that would have the initialization code. All you keep posting is out of context code snippets.

 

[MSAKARIM]

I don't think you have ever posted your RAM code that would have the initialization code. All you keep posting is out of context code snippets.

I used two templates of RAMs alternatively:
the first gives initial ram_out at addr=0 and start comparison from this value, but in the algorithm, i need the first value of ram_out to be at the first calc. of M

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

entity BRAM_1 is
Port ( clk,en,we: in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (11 downto 0);
din : in STD_LOGIC_VECTOR (31 downto 0);
dout : out STD_LOGIC_VECTOR (31 downto 0));
end BRAM_1;

architecture Behavioral of BRAM_1 is

type TRam is array(0 to 3871) of std_logic_vector(31 downto 0);

impure function init_bram (ram_file_name : in string) return TRam is
file ramfile : text ;
variable line_read : line;
variable ram_to_return : TRam;
begin
    file_open(ramfile,"F:\RAM_0.txt",READ_MODE);
  --while not endfile(ramfile) loop
  for i in TRam'range loop
  readline(ramfile, line_read);
  hread(line_read, ram_to_return(i));
  end loop;
  --end loop;
  return ram_to_return;
end function;

signal Ram : TRam := init_bram("F:\RAM_0.txt");
signal read_addr : std_logic_vector(11 downto 0);
begin

process (clk)
begin

if (clk'event and clk = '1') then
if (en ='1') then
   if (we = '1') then
   RAM(conv_integer(addr)) <= din;
   end if;
    read_addr <= addr;
end if;
end if;
end process;
dout <= RAM(conv_integer(read_addr));
end Behavioral;

The second template, I entered the READ statement " dout <= RAM(conv_integer(read_addr));" inside the process and it gives me results in the image of the previous comment.

 

[FlyingDutch]

Hello @MSAKARIM,

one question: Do you have data in RAM sorted ascending? This is condition needed to "Binary Search" algoritm work properly.

Best Regards

 

[MSAKARIM]

Hello @MSAKARIM,

one question: Do you have data in RAM sorted ascending? This is condition needed to "Binary Search" algoritm work properly.

Best Regards

Yes, it is sorted ascending.
You can have a look here link to external file share deleted, file added to post.

 

[ads-ee]

U usually means you don't have something hooked up correctly and nothing is driving the signal at all from the start of simulation. You might want to verify that the BRAM_1 instance is connected correctly.

Also have you verified there is something in the Ram signal? Have you brought that signal up in the simulation to make sure it gets loaded at the start of simulation?

 

[MSAKARIM]

U usually means you don't have something hooked up correctly and nothing is driving the signal at all from the start of simulation. You might want to verify that the BRAM_1 instance is connected correctly.

Also have you verified there is something in the Ram signal? Have you brought that signal up in the simulation to make sure it gets loaded at the start of simulation?

Really I can't catch where is the error exactly, is it in the original code or the simulation way!

 

[ads-ee]

With the bus being U it is likely a missing connection, probably a typo.

 

[MSAKARIM]

With the bus being U it is likely a missing connection, probably a typo.

By using the previously mentioned RAM template in post #49, it now gives initial ram_out at addr=0 and start comparison from this value, but in the algorithm, I need the first value of ram_out to be at the first calc. of M

 

[MSAKARIM]

Here is the simulation at different times
Ram_out takes the first value of the RAM contents (at addr =0) and maintain it all the time, although M_addr takes more values, so Ram_out should be changed at each Rising edge with the new content.

 

[dpaul]

Well then you have to debug why your RAM read fails. You have to check if your RTL read logic is working correctly or not.
I would suggest to write a simple test bench in which you enable the ram and then using a count-up counter, feed the incrementing read_addr to the ram and check if you get the expected data out.

 

[MSAKARIM]

Well then you have to debug why your RAM read fails. You have to check if your RTL read logic is working correctly or not.
I would suggest to write a simple test bench in which you enable the ram and then using a count-up counter, feed the incrementing read_addr to the ram and check if you get the expected data out.

I tested it lonely it works well, but inside the overall RTL it doesn't.

 

[dpaul]

Ok, show me the SS of the simulation waveform, when your SM places the read address the 1st memory location and drives the en signal high.
I want to see what is happening from the beginning when you enable the memory and place the first read address. The SS should also show the 5-6 following states.
Please post it in a resolution such that the signal transitions are comprehensible from the SS.